ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 80

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
Watchdog Timer Operation
Enabling and Disabling the WDT
The Watchdog Timer is disabled upon a RESET. To enable the WDT, the application
program must set the WDT_EN bit (bit 7) of the WDT_CTL register. When enabled, the
WDT cannot be disabled without a RESET.
Time-Out Period Selection
There are four choices of time-out periods for the WDT—2
clock cycles. The WDT time-out period is defined by the WDT_PERIOD field of the
WDT_CTL register (WDT_CTL[1:0]). The approximate time-out period for two
different WDT clock sources is listed in
Table 26. Watchdog Timer Approximate Time-Out Delays
RESET Or NMI Generation
On a WDT time-out, the RST_FLAG bit in the WDT_CTL register is set to 1. In addition,
the WDT can cause a RESET or send a nonmaskable interrupt (NMI) signal to the CPU.
The default operation is for the WDT to cause a RESET. It asserts/deasserts on the rising
edge of the clock. The RST_FLAG bit can be polled by the CPU to determine the source
of the RESET event.
Clock Source
32.768 kHz Crystal Oscillator
32.768 kHz Crystal Oscillator
32.768 kHz Crystal Oscillator
32.768 kHz Crystal Oscillator
20 MHz System Clock
20 MHz System Clock
20 MHz System Clock
20 MHz System Clock
50 MHz System Clock
50 MHz System Clock
50 MHz System Clock
50 MHz System Clock
Note: *WDT time-out values should be sufficiently long to allow Flash
operations to complete.
Divider Value
2
2
2
2
2
2
2
2
2
2
2
2
18
22
25
27
18
22
25
27
18
22
25
27
Table
26.
Time Out Delay
209.7 ms*
13.1 ms*
83.9 ms
4096 s
5.2 ms
1024 s
1.68 s
6.71 s
0.67 s
2.68 s
8.00 s
128 s
18
, 2
22
Product Specification
, 2
25
eZ80F92/eZ80F93
, and 2
Watchdog Timer
27
system
73