ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 132

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
UART_TxD
Baud Rate
Transmit
Receive
IR_TxD
7-clock
Clock
delay
endec. See Universal Asynchronous Receiver/Transmitter on page 104 for more informa-
tion about the UART and its Baud Rate Generator.
The data to be transmitted via the IR transceiver is first sent to UART0. The UART trans-
mit signal (TxD) and Baud Rate Clock are used by the IrDA endec to generate the modu-
lation signal (IR_TxD) that drives the infrared transceiver. To enable transmit encoding,
the IR_RxEN bit in the IR_CTL register must be set to 0.
Each UART bit is 16-clocks wide. If the data to be transmitted is a logical 1 (High), the
IR_TxD signal remains Low (0) for the full 16-clock period. If the data to be transmitted is
a logical 0, a 3-clock High (1) pulse is output following a 7-clock Low (0) period. Follow-
ing the 3-clock High pulse, a 6-clock Low pulse completes the full 16-clock data period.
Data transmission is displayed in
function should be disabled by clearing the IR_RxEN bit in the IR_CTL reg to 0. The SIR
data format uses half-duplex communication; the UART does not transmit data while the
receiver decoder is enabled.
Data is received from the IR transceiver via the IR_RxD signal and decoded by the IrDA
endec. This decoded data is passed from the endec to UART0. To enable receiver decode,
the IR_RxEN bit in the IR_CTL register must be set to 1. The SIR data format uses half-
duplex communication; therefore, the UART should not transmit data during normal oper-
ation while the receiver decoder is enabled.
Start Bit = 0
16-clock
period
3-clock
pulse
Figure 27.Infrared Data Transmission
Data Bit 0 = 1
Figure
Data Bit 1 = 0
27. During data transmission, the IR receive
Data Bit 2 = 1
Product Specification
Infrared Encoder/Decoder
Data Bit 3 = 1
125