ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 134

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
Receiver Frequency Divider
Table 67. IrDA Physical Layer 1.4 Pulse Durations Specifications (Continued)
The IrDA receiver uses a 6-bit frequency divider. The value is derived from the system
clock to measure IR_RxD pulses. The IrDA endec detects pulses that are within the IrDA
Physical Layer specified minimum and maximum ranges, with system clock frequencies
from 5 MHz up to 50 MHz.
The upper four bits of the frequency divider factor are set via the FREQ_DIV bit in the
IR_CTL register, based on the following equation:
The remaining lower two bits of the divider are set to
sponds to a period of 1.2 seconds. The FREQ_DIV value must be rounded to the nearest
integer and the resulting period of the 6-bit frequency divider must not be larger than
1.4 seconds, which is the IrDA defined minimum pulse width. If the period is greater than
1.4 seconds, FREQ_DIV should be rounded to the next lower integer. The receiver fre-
quency divider value versus the system clock frequency is shown in table, below.
Table 68. Frequency Divider Values
Frequency Divider Factor =
System Clock
< 5.0 MHz
5.0–7.8 MHz
7.8–10.8 MHz
10.8–13.6 MHz
13.6–25 MHz
25–50 MHz
Note: *The frequency divider is disabled when set to 00h.
Baud Rate
115200
57600
FREQ_DIV
00h*
01h
02h
03h
FLOOR[4-bit Frequency Divider Factor]
ROUND[4-bit Frequency Divider Factor]
Minimum Pulse
Width
1.41 s
1.41 s
System Clock Frequency (MHz)
Target Frequency of 3.33 MHz
Maximum Pulse
Width
4.34 s
2.23 s
03h
. The target frequency corre-
Product Specification
Infrared Encoder/Decoder
127