ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 153
ez80f92
Manufacturer Part Number
ez80f92
Description
Ez80acclaim Flash Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80F92.pdf
(261 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ez80f92AZ020SG
Manufacturer:
Zilog
Quantity:
20
Company:
Part Number:
ez80f92AZ020SG
Manufacturer:
MAX
Quantity:
47
Company:
Part Number:
ez80f92AZ020SG
Manufacturer:
ZILOG
Quantity:
3
- Current page: 153 of 261
- Download datasheet (4Mb)
PS015313-0508
Operating Modes
In other words, arbitration is not allowed between:
•
•
•
Clock Synchronization for Handshake
The Clock synchronizing mechanism can function as a handshake, enabling receivers to
cope with fast data transfers, on either a byte or bit level. The byte level allows a device to
receive a byte of data at a fast rate, but allows the device more time to store the received
byte or to prepare another byte for transmission. Slaves hold the SCL line Low after recep-
tion and acknowledge the byte, forcing the master into a wait state until the slave is ready
for the next byte transfer in a handshake procedure.
Master Transmit
In MASTER TRANSMIT mode, the I
Enter MASTER TRANSMIT mode by setting the STA bit in the I2C_CTL register to 1.
The I
When a START condition is transmitted, the IFLG bit is 1 and the status code in the
I2C_SR register is
loaded with either a 7-bit slave address or the first part of a 10-bit slave address, with the
lsb cleared to 0 to specify TRANSMIT mode. The IFLG bit should now be cleared to 0 to
prompt the transfer to continue.
After the 7-bit slave address (or the first part of a 10-bit address) plus the Write bit are
transmitted, the IFLG is set again. A number of status codes are possible in the I2C_SR
register. See
A repeated START condition and a data bit
A STOP condition and a data bit
A repeated START condition and a STOP condition
2
C then tests the I
Table 78
08h
on page 147.
2
. Before this interrupt is serviced, the I2C_DR register must be
C bus and transmits a START condition when the bus is free.
2
C transmits a number of bytes to a slave receiver.
Product Specification
I2C Serial I/O Interface
146
Related parts for ez80f92
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
Manufacturer:
ZiLOG Semiconductor
Datasheet:
Part Number:
Description:
Ez80f91 Mini Enet Module
Manufacturer:
ZiLOG Semiconductor
Datasheet:
Part Number:
Description:
Z90233, Z90234, And Z90231 Ezvision 200 Television Controller
Manufacturer:
ZiLOG Semiconductor
Datasheet:
Part Number:
Description:
Digital Television Controllers
Manufacturer:
ZiLOG Semiconductor
Datasheet:
Part Number:
Description:
Television Controllers
Manufacturer:
ZiLOG Semiconductor
Datasheet:
Part Number:
Description:
40-pin Low-cost Digital Television Controller
Manufacturer:
ZiLOG Semiconductor
Datasheet:
Part Number:
Description:
40-pin Low-cost Digital Television Controller
Manufacturer:
ZiLOG Semiconductor
Datasheet:
Part Number:
Description:
Digital Television Controller In-circuit Emulator Ice Device
Manufacturer:
ZiLOG Semiconductor
Datasheet:
Part Number:
Description:
Digital Television Controller
Manufacturer:
ZiLOG Semiconductor
Datasheet:
Part Number:
Description:
Digital Television Controller
Manufacturer:
ZiLOG Semiconductor
Datasheet:
Part Number:
Description:
High Performance Microcontrollers
Manufacturer:
ZiLOG Semiconductor
Datasheet:
Part Number:
Description:
Cmos Usc Universal Serial Controller
Manufacturer:
ZiLOG Semiconductor
Datasheet:
Part Number:
Description:
Iusc Integrated Universal Serial Controller
Manufacturer:
ZiLOG Semiconductor
Datasheet:
Part Number:
Description:
16-bit Processor
Manufacturer:
ZiLOG Semiconductor
Datasheet:
Part Number:
Description:
Pcmcia Interface Solution
Manufacturer:
ZiLOG Semiconductor
Datasheet: