ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 74

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

Table 22. Chip Select x Lower Bound Register(CS0_LBR = 00A8h, CS1_LBR = 00ABh, CS2_LBR =
PS015313-0508
Chip Select Registers
Chip Select x Lower Bound Register
For Memory Chip Selects, the Chip Select x Lower Bound register, listed in
defines the lower bound of the address range for which the corresponding Memory Chip
Select (if enabled) can be active. For I/O Chip Selects, this register defines the address to
which ADDR[15:8] is compared to generate an I/O Chip Select. All Chip Select lower
bound registers reset to
00AEh, CS3_LBR = 00B1h)
Bit
CS0_LBR Reset
CS1_LBR Reset
CS2_LBR Reset
CS3_LBR Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
CSx_LBR
Value Description
00h–
FFh
For Memory Chip Selects (
This byte specifies the lower bound of the Chip Select address
range. The upper byte of the address bus, ADDR[23:16], is
compared to the values contained in these registers for
determining whether a Memory Chip Select signal should be
generated.
For I/O Chip Selects (
This byte specifies the Chip Select address value. ADDR[15:8] is
compared to the values contained in these registers for
determining whether an I/O Chip Select signal should be
generated.
00h
R/W
.
7
0
0
0
0
R/W
6
0
0
0
0
R/W
5
0
0
0
0
CSX_IO
R/W
CSX_IO
4
0
0
0
0
= 1)
R/W
3
0
0
0
0
= 0)
Chip Selects and Wait States
Product Specification
R/W
2
0
0
0
0
eZ80F92/eZ80F93
R/W
Table
1
0
0
0
0
22,
R/W
0
0
0
0
0
67