ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 191
ez80f92
Manufacturer Part Number
ez80f92
Description
Ez80acclaim Flash Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80F92.pdf
(261 pages)
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PS015313-0508
ZDI Read Register Low, High, and Upper
The ZDI register Read Only address space offers Low, High, and Upper functions, which
contain the value read by a Read operation from the ZDI Read/Write Control register
(ZDI_RW_CTL). This data is valid only while in ZDI BREAK mode and only if the
instruction is read by a request from the ZDI Read/Write Control register. See
Table 107. ZDI Read Register Low, High and Upper(ZDI_RD_L = 10h, ZDI_RD_H =
11h, and ZDI_RD_U = 12h in the ZDI Register Read Only Address Space)
Bit
Position
4
ADL
3
MADL
2
IEF1
[1:0]
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:0]
ZDI_RD_L,
ZDI_RD_H, or
ZDI_RD_U
Value Description
0
1
0
1
0
1
00
Value Description
00h–
FFh
R
7
0
The CPU is operating in Z80
(ADL bit = 0)
The CPU is operating in ADL MEMORY mode.
(ADL bit = 1)
The CPU’s Mixed-Memory mode (MADL) bit is reset to 0.
The CPU’s Mixed-Memory mode (MADL) bit is set to 1.
The CPU’s Interrupt Enable Flag 1 is reset to 0. Maskable
interrupts are disabled.
The CPU’s Interrupt Enable Flag 1 is set to 1. Maskable
interrupts are enabled.
Reserved.
Values read from the memory location as requested by the
ZDI Read Control register during a ZDI Read operation.
The 24-bit value is supplied by {ZDI_RD_U, ZDI_RD_H,
ZDI_RD_L}.
R
6
0
R
5
0
R
4
0
®
R
3
0
MEMORY mode.
Product Specification
R
2
0
eZ80F92/eZ80F93
Zilog Debug Interface
R
1
0
Table
107.
R
0
0
184
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