AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 98
AT90PWM81
Manufacturer Part Number
AT90PWM81
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT90PWM161.pdf
(325 pages)
Specifications of AT90PWM81
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
20
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
8
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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11.8.5
98
AT90PWM81
Timer/Counter1 Interrupt Flag Register – TIFR1
• Bit 7, 6 – Res: Reserved Bits
These bits are unused bits in the AT90PWM81, and will always read as zero.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see XXXX) is
executed when the ICF1 Flag, located in TIFR1, is set.
• Bit 4, 3, 2,1 – Res: Reserved Bits
These bits are unused bits in the AT90PWM81, and will always read as zero.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (see
61) is executed when the TOV1 Flag, located in TIFR1, is set.
• Bit 7, 6 – Res: Reserved Bits
These bits are unused bits in the AT90PWM81, and will always read as zero.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is
set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP
value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1
can be cleared by writing a logic one to its bit location.
• Bit 4, 3, 2,1 – Res: Reserved Bits
• Bit 0 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WG.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alterna-
tively, TOV1 can be cleared by writing a logic one to its bit location.
Bit
Read/Write
Initial Value
7
–
R
0
R
6
–
0
5
ICF1
R/W
0
4
–
R
0
3
–
R
0
2
–
R/W
0
1
–
R/W
0
0
TOV1
R/W
0
Table 8-1 on page
7734P–AVR–08/10
TIFR1
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