AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 144
AT90PWM81
Manufacturer Part Number
AT90PWM81
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT90PWM161.pdf
(325 pages)
Specifications of AT90PWM81
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
20
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
8
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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12.26.3
144
AT90PWM81
PSC2 Interrupt Flag Register – PIFR2
Bit
Read/Write
Initial Value
• Bit 7 – POACnB : PSC n Output B Activity
This bit is set by hardware each time the output PSCOUTn1 changes from 0 to 1 or from 1 to 0.
Must be cleared by software by writing a one to its location.
This feature is useful to detect that a PSC output doesn’t change due to a frozen external input signal.
• Bit 6 – POACnA : PSC n Output A Activity
This bit is set by hardware each time the output PSCOUTn0 changes from 0 to 1 or from 1 to 0.
Must be cleared by software by writing a one to its location.
This feature is useful to detect that a PSC output doesn’t change due to a frozen external input signal.
• Bit 5 – PSEIn : PSC n Synchro Error Interrupt
This bit is set by hardware when the update (or end of PSC cycle) of the PSCn configured in auto run
(PARUNn = 1) does not occur at the same time than the PSCn-1 which has generated the input run signal.
(For PSC0, PSCn-1 is PSC2).
Must be cleared by software by writing a one to its location.
This feature is useful to detect that a PSC doesn’t run at the same speed or with the same phase than the
PSC master.
• Bit 4 – PEVnB : PSC n External Event B Interrupt
This bit is set by hardware when an external event which can generates a capture or a retrigger from
Retrigger/Fault block B occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVEnB bit = 0).
• Bit 3 – PEVnA : PSC n External Event A Interrupt
This bit is set by hardware when an external event which can generates a capture or a retrigger from
Retrigger/Fault block A occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVEnA bit = 0).
• Bit 2:1 – PRNn1:0 : PSC n Ramp Number
Memorization of the ramp number when the last PEVnA or PEVnB occurred .
7
POAC2B
R
0
6
POAC2A
R
0
5
PSEI2
R/W
0
4
PEV2B
R/W
0
3
PEV2A
R/W
0
2
PRN21
R
0
1
PRN20
R
0
0
PEOP2
R/W
0
7734P–AVR–08/10
PIFR2
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