AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 135

• Manufacturer Part Number: AT90PWM81
• Manufacturer: Atmel Corporation

Specifications of AT90PWM81

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.25.4
12.25.5
12.25.6
7734P–AVR–08/10
Output Compare SB Register – OCRnSBH and OCRnSBL
Output Compare RB Register – OCRnRBH and OCRnRBL
PSC 2 Configuration Register – PCNF2
Note : n = 0 to 2 according to PSC number.
The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously compared
with the PSC counter value. A match can be used to generate an Output Compare interrupt, or to generate
a waveform output on the associated pin.
The Output Compare Registers RB contains also a 4-bit value that is used for the flank width modulation.
The Output Compare Registers are 16bit and 12-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit tem-
porary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers.
The PSC n Configuration Register is used to configure the running mode of the PSC.
• Bit 7 - PFIFTYn: PSC n Fifty
Writing this bit to one, set the PSC in a fifty percent mode where only OCRnRBH/L and OCRnSBH/L are
used. They are duplicated in OCRnRAH/L and OCRnSAH/L during the update of OCRnRBH/L. This fea-
ture is useful to perform fifty percent waveforms.
• Bit 6 - PALOCKn: PSC n Autolock
When this bit is set, the Output Compare Registers RA, SA, SB, the Output Matrix POM2 and the PSC
Output Configuration PSOCn can be written without disturbing the PSC cycles. The update of the PSC
internal registers will be done at the end of the PSC cycle if the Output Compare Register RB has been the
last written.
When set, this bit prevails over LOCK (bit 5)
• Bit 5 – PLOCKn: PSC n Lock
When this bit is set, the Output Compare Registers RA, RB, SA, SB, the Output Matrix POM2 and the
PSC Output Configuration PSOCn can be written without disturbing the PSC cycles. The update of the
PSC internal registers will be done if the LOCK bit is released to zero.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
7
PFIFTY2
R/W
0
7
–
OCRnSB[7:0]
W
0
7
OCRnRB[15:12]
OCRnRB[7:0]
W
0
6
–
W
0
6
W
0
6
PALOCK2 PLOCK2
R/W
0
5
–
W
0
5
W
0
5
R/W
0
0
0
4
PMODE21 PMODE20 POP2
R/W
0
4
–
W
4
W
3
R/W
0
3
OCRnSB[11:8]
W
0
3
OCRnRB[11:8]
W
0
2
R/W
0
2
W
0
2
W
0
1
PCLKSEL2 POME2
R/W
0
1
W
0
1
W
0
AT90PWM81
0
R/W
0
0
W
0
0
W
0
PCNF2
OCRnSBH
OCRnSBL
OCRnRBH
OCRnRBL
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