AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 178

• Manufacturer Part Number: AT90PWM81
• Manufacturer: Atmel Corporation

Specifications of AT90PWM81

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

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AT90PWM81
PSCR Interrupt Flag Register – PIFR0
• Bit 2 – Reserved
• Bit 1– PEOEPE0 : PSCR End Of Enhanced Cycle Interrupt Enable
When this bit is set, an interrupt is generated when PSC reduced reaches the end of the 15th PSC cycle.
This allows to update the PSCR values in the interrupt routine and to start a new enhanced cycle with the
new values at the next PSCR cycle end.
• Bit 0 – PEOPE0 : PSCR End Of Cycle Interrupt Enable
When this bit is set, an interrupt is generated when PSCR reaches the end of the whole cycle.
Bit
Read/Write
Initial Value
• Bit 7 – POAC0B : PSCR Output B Activity
This bit is set by hardware each time the output PSCOUT01 changes from 0 to 1 or from 1 to 0.
Must be cleared by software by writing a one to its location.
This feature is useful to detect that a PSCR output doesn’t change due to a frozen external input signal.
• Bit 6 – POAC0A : PSCR Output A Activity
This bit is set by hardware each time the output PSCOUT00 changes from 0 to 1 or from 1 to 0.
Must be cleared by software by writing a one to its location.
This feature is useful to detect that a PSCR output doesn’t change due to a freezen external input signal.
• Bit 5 – Reserved
• Bit 4 – PEV0B : PSCR External Event B Interrupt
This bit is set by hardware when an external event which can generates a capture or a retrigger from
Retrigger/Fault block B occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVE0B bit = 0).
• Bit 3 – PEV0A : PSCR External Event A Interrupt
This bit is set by hardware when an external event which can generates a capture or a retrigger from
Retrigger/Fault block A occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVE0A bit = 0).
• Bit 2:1 – PRN01:0 : PSCR Ramp Number
Memorization of the ramp number when the last PEV0A or PEV0B occurred.
7
POAC0B
R
0
6
POAC0A
R
0
5
-
R
0
4
PEV0B
R/W
0
3
PEV0A
R/W
0
2
PRN01
R
0
1
PRN00
R
0
0
PEOP0
R/W
0
7734P–AVR–08/10
PIFR0