AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 228

• Manufacturer Part Number: AT90PWM81
• Manufacturer: Atmel Corporation

Specifications of AT90PWM81

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

18.3.1
18.4
18.4.1
228
DAC Register Description
AT90PWM81
DAC Voltage Reference
Digital to Analog Conversion Control Register – DACON
disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without
causing an interrupt. However, the interrupt flag must be cleared in order to trigger a new conversion at
the next interrupt event.
The reference voltage for the ADC (V
selected as either AV
AV
the internal bandgap reference (V
nected to the DAC, the reference voltage can be made more immune to noise by connecting a capacitor
between the AREF pin and ground. V
voltmeter. Note that V
system.
The user may switch between AV
result after switching reference voltage source may be inaccurate, and the user is advised to discard this
result.
The DAC is controlled via three dedicated registers:
• Bit 7 – DAATE: DAC Auto Trigger Enable bit (not useful, may be left for compatibility)
Set this bit to update the DAC input value on the positive edge of the trigger signal selected with the
DACTS2-0 bit in DACON register.
Clear it to automatically update the DAC input when a value is written on DACH register.
• Bit 6:4 – DATS2, DATS1, DATS0: DAC Trigger Selection bits (not useful, may be left for
These bits are only necessary in case the DAC works in auto trigger mode. It means if DAATE bit is set.
In accordance with the
the DAC input values. The update will be generated by the rising edge of the selected interrupt flag
whether the interrupt is enabled or not.
Table 18-1.
Bit
Read/Write
Initial Value
DATS2
0
0
0
0
• The DACON register which is used for DAC configuration
• DACH and DACL which are used to set the value to be converted.
compatibility)
CC
is connected to the DAC through a passive switch. The internal 2.56V reference is generated from
DATS1
0
0
1
1
7
DAATE
R/W
0
DAC Auto Trigger source selection
CC
REF
Table
, internal 2.56V reference, or external AREF pin.
is a high impedance source, and only a capacitive load should be connected in a
6
DATS2
R/W
0
DATS0
0
1
0
1
18-1, these 3 bits select the interrupt event which will generate the update of
BG
CC,
5
DATS1
R/W
0
) through an internal amplifier. When the external AREF pin is con-
AVCC and 2.56V as reference selection. The first DAC conversion
REF
REF
Description
Analog comparator 0
Analog comparator 1
External Interrupt Request 0
Reserved
can also be measured at the AREF pin with a high impedance
) indicates the conversion range for the DAC. V
4
DATS0
R/W
0
3
-
-
0
2
DALA
R/W
0
1
-
-
0
0
DAEN
R/W
0
7734P–AVR–08/10
REF
DACON
can be