AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 92

• Manufacturer Part Number: AT90PWM81
• Manufacturer: Atmel Corporation

Specifications of AT90PWM81

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11.5.1
92
AT90PWM81
Input Capture Trigger Source
Figure 11-4.
When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively on the
Analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture
will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the
Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the
TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1), the Input Capture Flag generates an
Input Capture interrupt. The ICF1 Flag is automatically cleared when the interrupt is executed. Alterna-
tively the ICF1 Flag can be cleared by software by writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low byte
(ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied into the high
byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP
Register.
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1
Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13)
bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Regis-
ter the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L.
For more information on how to access the 16-bit registers refer to
86.
The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Timer/Counter1 can
alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog
Comparator is selected as trigger source by setting the Analog Comparator Input Capture (AC1ICE) bit in
the Analog Comparator Extended Control Register (AC1ECON). Be aware that changing trigger source
can trigger a capture. The Input Capture Flag must therefore be cleared after the change.
WRITE
Input Capture Unit Block Diagram
ICPnA
ICRnH (8-bit)
TEMP (8-bit)
ICRn (16-bit Register)
ICRnL (8-bit)
DATA BUS
Canceler
Noise
ICNC
(8-bit)
TCNTnH (8-bit)
TCNTn (16-bit Counter)
“Accessing 16-bit Registers” on page
Detector
ICES
Edge
TCNTnL (8-bit)
ICFn (Int.Req.)
7734P–AVR–08/10