AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 64

• Manufacturer Part Number: AT90PWM81
• Manufacturer: Atmel Corporation

Specifications of AT90PWM81

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

8.1.1
8.1.2
64
AT90PWM81
Moving Interrupts Between Application and Boot Space
MCU Control Register – MCUCR
The MCU Control Register controls the placement of the Interrupt Vector table.
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory.
When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of
the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses.
Refer to the section
details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be fol-
lowed to change the IVSEL bit:
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the
cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If
IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaf-
fected by the automatic disabling.
Note:
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hard-
ware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts,
as explained in the IVSEL description above. See Code Example below.
Bit
Read/Write
Initial Value
.org 0xC00
0xC00
0xC01
0xC02
...
0xC1F
;
0xC20
0xC21
0xC22
0xC23
0xC24
0xC25
a.
b.
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, inter-
rupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the
Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from
the Boot Loader section. Refer to the section
ming” on page 232
Write the Interrupt Vector Change Enable (IVCE) bit to one.
Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
RESET: ldi
7
–
R
0
“Boot Loader Support – Read-While-Write Self-Programming” on page 232
rjmp
rjmp
rjmp
...
rjmp
out
ldi
out
sei
<instr>
6
–
R
0
for details on Boot Lock bits.
RESET
PSC2_CAPT
PSC2_EC
...
SPM_RDY
r16,high(RAMEND); Main program start
SPH,r16
r16,low(RAMEND)
SPL,r16
5
–
R
0
xxx
4
PUD
R/W
0
“Boot Loader Support – Read-While-Write Self-Program-
; Reset handler
; PSC2 Capture event Handler
; PSC2 End Cycle Handler
;
; Store Program Memory Ready Handler
; Set Stack Pointer to top of RAM
; Enable interrupts
3
RSTDIS
R/W
0
2
CKRC81
R/W
0
1
IVSEL
R/W
0
0
IVCE
R/W
0
7734P–AVR–08/10
MCUCR
for