AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 172
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AT90PWM81
Manufacturer Part Number
AT90PWM81
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT90PWM161.pdf
(325 pages)
Specifications of AT90PWM81
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
20
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
8
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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13.23.2
13.23.3
13.23.4
172
AT90PWM81
Output Compare SA Register – OCR0SAH and OCR0SAL
Output Compare RA Register – OCR0RAH and OCR0RAL
Output Compare SB Register – OCR0SBH and OCR0SBL
• Bit 5:4 – PSYNC01:0: Synchronization Out for ADC Selection)
Select the polarity and signal source for generating a signal which will be sent to the ADC for
synchronization.
Table 13-10.
• Bit 3 – Reserved.
• Bit 2 – POEN0B: PSCR OUT Part B Output Enable
When this bit is clear, I/O pin affected to PSCOUT01 acts as a standard port.
When this bit is set, I/O pin affected to PSCOUT01 is connected to the PSCR waveform generator B out-
put and is set and clear according to the PSCR operation.
• Bit 1 – Reserved
• Bit 0 – POEN0A: PSCR OUT Part A Output Enable
When this bit is clear, I/O pin affected to PSCOUT00 acts as a standard port.
When this bit is set, I/O pin affected to PSCOUT00 is connected to the PSCR waveform generator A out-
put and is set and clear according to the PSCR operation.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
PSYNC01
0
0
1
1
7
–
OCR0SA[7:0]
W
0
7
–
OCR0RA[7:0]
W
0
7
–
OCR0SB[7:0]
W
0
Synchronization Source Description in One/Two/Four Ramp Modes
PSYNC00
0
1
0
1
6
–
W
0
6
–
W
0
6
–
W
0
Description
Send signal on leading edge of PSCOUT00 (match with OCR0SA)
Send signal on trailing edge of PSCOUT00 (match with OCR0RA or
fault/retrigger on part A)
Send signal on leading edge of PSCOUT01 (match with OCR0SB)
Send signal on trailing edge of PSCOUT01 (match with OCR0RB or
fault/retrigger on part B)
5
–
W
0
5
–
W
0
5
–
W
0
4
–
W
0
4
–
W
0
4
–
W
0
3
OCR0SA[11:8]
W
0
3
OCR0RA[11:8]
W
0
3
OCR0SB[11:8]
W
0
2
W
0
2
W
0
2
W
0
1
W
0
1
W
0
1
W
0
0
W
0
0
W
0
0
W
0
7734P–AVR–08/10
OCR0SAH
OCR0SAL
OCR0RAH
OCR0RAL
OCR0SBH
OCR0SBL
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