AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 121

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AT90PWM81

Manufacturer Part Number
AT90PWM81
Description
Manufacturer
Atmel Corporation
Datasheet

Specifications of AT90PWM81

Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
20
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
8
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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12.10 PSC Input Mode 2: Stop signal, Execute Opposite Pulse and Wait
7734P–AVR–08/10
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
DT0
DT0
OT0
OT0
Figure 12-24. PSCn behavior versus PSCn Input A in Fault Mode 2
PSC Input A is take into account during DT0 and OT0 only. It has no effect during DT1 and OT1.
When PSCn Input A event occurs, PSC releases PSCOUTn0, jumps and executes DT1 plus OT1 and then
waits for PSC Input A inactive state.
Even if PSC Input A is released during DT1 or OT1, DT1 plus OT1 sub-cycle is always completely
executed.
Figure 12-25. PSCn behavior versus PSCn Input B in Fault Mode 2
PSC Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and OT0.
When PSC Input B event occurs, PSC releases PSCOUTn1, jumps and executes DT0 plus OT0 and then
waits for PSC Input B inactive state.
Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always completely
executed.
DT1
DT1
OT1
OT1
DT0
DT0 OT0 DT1
OT0
DT1
OT1
OT1
DT0
OT0
DT0
OT0
AT90PWM81
DT1
DT1
OT1
OT1
121

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