AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 85
AT90PWM81
Manufacturer Part Number
AT90PWM81
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT90PWM161.pdf
(325 pages)
Specifications of AT90PWM81
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
20
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
8
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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11.1.1
7734P–AVR–08/10
Registers
Figure 11-1.
Note:
The Timer/Counter (TCNT1), and Input Capture Register (ICR1) are all 16-bit registers. Special proce-
dures must be followed when accessing the 16-bit registers. These procedures are described in the section
“Accessing 16-bit Registers” on page
registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) sig-
nals are all visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually masked
with the Timer Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure.
The Timer/Counter can be clocked internally, or by an external clock source on the T1 pin. The Clock
Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decre-
ment) its value. The Timer/Counter is inactive when no clock source is selected. The output from the
Clock Select logic is referred to as the timer clock (clk
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event
on either the Input Capture pin (ICP1). The Input Capture unit includes a digital filtering unit (Noise Can-
celer) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by the
ICR1 Register, or by a set of fixed values.
1. Refer to
16-bit Timer/Counter Block Diagram
Table 2-1 on page 5
Timer/Counter
TCNTn
ICRn
Count
Clear
86. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit
for Timer/Counter1 pin placement and description.
Control Logic
TOP
=
TCCRnB
Values
BOTTOM
(1)
Fixed
TOP
T
ICFn (Int.Req.)
1
).
clk
Detector
Edge
=
Tn
0
TOVn
(Int.Req.)
Clock Select
(Ckio )
Canceler
Detector
Noise
Edge
AT90PWM81
Comparator Ouput )
AC1ICE
( From Analog
ICPn
Tn
85
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