AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 128
AT90PWM81
Manufacturer Part Number
AT90PWM81
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT90PWM161.pdf
(325 pages)
Specifications of AT90PWM81
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
20
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
8
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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Price
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12.18.1
12.18.2
12.18.3
128
AT90PWM81
Available Input Mode according to Running Mode
Event Capture
Using the Input Capture Unit
Some Input Modes are not consistent with some Running Modes. So the table below gives the input
modes which are valid according to running modes.
Table 12-8.
The PSC can capture the value of time (PSC counter) when a retrigger event or fault event occurs on PSC
inputs. This value can be read by software in PICRnH/L register.
The main challenge when using the Input Capture unit is to assign enough processor capacity for handling
the incoming events. The time between two events is critical. If the processor has not read the captured
value in the PICR1 Register before the next event occurs, the PICR1 will be overwritten with a new value.
In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the PICR1 Register should be read as early in the interrupt han-
dler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum
interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the
other interrupt requests.
Input Mode Number
:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Available Input Modes according to Running Modes
1 Ramp Mode
Valid
Do not use
Do not use
Valid
Do not use
Do not use
Valid
Valid
Valid
Do not use
Valid
Do not use
2 Ramp Mode
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
4 Ramp Mode
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Centered Mode
Do not use
Do not use
Do not use
Valid
Do not use
Do not use
Valid
Do not use
Do not use
Do not use
7734P–AVR–08/10
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