AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 208

• Manufacturer Part Number: AT90PWM81
• Manufacturer: Atmel Corporation

Specifications of AT90PWM81

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.5
208
Changing Channel or Reference Selection
AT90PWM81
Figure 17-6.
Figure 17-7.
Table 17-1.
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to
which the CPU has random access. This ensures that the channels and reference selection only takes place
at a safe point during the conversion. The channel and reference selection is continuously updated until a
conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a
sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before
the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following ris-
ing ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference
selection values to ADMUX until one ADC clock cycle after ADSC is written.
Condition
Sample & Hold
(Cycles from Start of Conversion)
Conversion Time
(Cycles)
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
ADC Timing Diagram, Auto Triggered Conversion
ADC Timing Diagram, Free Running Conversion
ADC Conversion Time
Prescaler
Reset
MUX and REFS
Update
1
2
3
Sample &
Hold
4
5
First Conversion
6
13.5
7
25
One Conversion
8
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Conversion
13
Conversion
Complete
Complete
One Conversion
14
14
Conversion, Single
15
15
Normal
Ended
15.5
16
16
3.5
Next Conversion
1
Sign and MSB of Result
Sign and MSB of Result
LSB of Result
LSB of Result
2
MUX and REFS
Update
Next Conversion
1
Prescaler
Reset
3
Sample & Hold
2
4
Auto Triggered
Conversion
7734P–AVR–08/10
16
4