AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 155

• Manufacturer Part Number: AT90PWM81
• Manufacturer: Atmel Corporation

Specifications of AT90PWM81

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

13.6.1
13.7
13.8
7734P–AVR–08/10
Enhanced resolution
PSCR Inputs
Value Update Synchronization
Figure 13-7.
The software can stop the cycle before the end to update the values and restart a new PSCR cycle.
New timing values or PSCR output configuration can be written during the PSCR cycle. Thanks to LOCK
and AUTOLOCK configuration bits, the new whole set of values can be taken into account with the fol-
lowing conditions:
The registers which update is synchronized thanks to LOCK and AUTOLOCK are OCRrSAH/L, OCR-
rRAH/L, OCRrSBH/L, OCRrRBH/L and PSOCr. PISELrA1 and PISELrB1 bits of PSOCr are
immediatly updated in order to behave as PISELrA0 and PISELrB0.
See these register’s description starting on
When set, AUTOLOCK configuration bit prevails over LOCK configuration bit.
See “PSCR Configuration Register – PCNF0” on page 173.
The PSCR includes the same resolution enhancement as in PSC. Please see Section “Enhanced Resolu-
tion”, page 110 for the description of this feature.
Each part A or B of PSCR has its own system to take into account one PSCR input. According to PSCR
Input A/B Control Register (see description
Fault input.
This system A or B is also configured by this PSCR Input A/B Control Register (PFRCrA/B).
Software
PSC
• When AUTOLOCK configuration is selected, the update of the PSCR internal registers will be done at
• When LOCK configuration bit is set, there is no update. The update of the PSCR internal registers will
the end of the PSCR cycle following a write in the Output Compare Register RB. The AUTOLOCK
configuration bit is taken into account at the end of the first PSCR cycle.
be done at the end of the PSCR cycle if the LOCK bit is released to zero.
Regulation Loop
Calculation
Cycle
With Set i
Update at the end of complete PSCR cycle.
Cycle
With Set i
Cycle
With Set i
Writting in
PSC Registers
page
13.23.8page
Cycle
With Set i
172.
End of Cycle
Request for
an Update
175), PSCrIN0/1 input can act has a Retrigger or
Cycle
With Set j
AT90PWM81
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