AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 142
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AT90PWM81
Manufacturer Part Number
AT90PWM81
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT90PWM161.pdf
(325 pages)
Specifications of AT90PWM81
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
20
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
8
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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12.25.12
12.26 PSC2 Specific Register
12.26.1
142
AT90PWM81
PSC 2 Input Capture Register – PICR2H and PICR2L
PSC 2 Output Matrix – POM2
Table 12-21.
• Bit 7 – PCSTn : PSC Capture Software Trig bit
Set this bit to trigger off a capture of the PSC counter. When reading, if this bit is set it means that the cap-
ture operation was triggered by PCSTn setting otherwise it means that the capture operation was triggered
by a PSC input.
The Input Capture is updated with the PSC counter value each time an event occurs on the enabled PSC
input pin (or optionally on the Analog Comparator output) if the capture function is enabled (bit PCAEnx
in PFRCnx register is set).
The Input Capture Register is 12-bit in size. To ensure that both the high and low bytes are read simultane-
ously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte
register (TEMP). This temporary register is shared by all the other 16-bit or 12-bit registers.
Bit
Read/Write
Initial Value
• Bit 7 – POMV2B3: Output Matrix Output B Ramp 3
This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 3
• Bit 6 – POMV2B2: Output Matrix Output B Ramp 2
This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 2
• Bit 5 – POMV2B1: Output Matrix Output B Ramp 1
This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 1
Bit
Read/Write
Initial Value
PRFMnx3:0
1010b
1011b
1100b
1101b
1110b
1111b
7
POMV2B3
R/W
0
7
PCST2
PICR2[7:0]
R
0
Level Sensitivity and Fault Mode Operation
Description
Reserved (do not use)
PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Deactivate Output
Reserved (do not use)
6
POMV2B2 POMV2B1 POMV2B0 POMV2A3 POMV2A2 POMV2A1 POMV2A0 POM2
R/W
0
6
–
R
0
5
R/W
0
5
–
R
0
4
R/W
0
4
–
R
0
3
R/W
0
3
PICR2[11:8]
R
0
2
R/W
0
2
R
0
R/W
1
0
1
R
0
0
R/W
0
0
R
0
7734P–AVR–08/10
PICR2H
PICR2L
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