AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 66

• Manufacturer Part Number: AT90PWM81
• Manufacturer: Atmel Corporation

Specifications of AT90PWM81

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

9.
9.1
66
I/O-Ports
Introduction
AT90PWM81
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This
means that the direction of one port pin can be changed without unintentionally changing the direction of
any other pin with the SBI and CBI instructions. The same applies when changing drive value (if config-
ured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has
symmetrical drive characteristics with both high sink and source capability. All port pins have individu-
ally selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection
diodes to both V
273
Figure 9-1.
All registers and bit references in this section are written in general form. A lower case “x” represents the
numbering letter for the port, and a lower case “n” represents the bit number. However, when using the
register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in
Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in
“Register Description for I/O-Ports”.
Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx,
Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read
only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one
to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addi-
tion, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when
set.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O”. Most port pins are
multiplexed with alternate functions for the peripheral features on the device. How each alternate function
interferes with the port pin is described in
module sections for a full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins
in the port as general digital I/O.
for a complete list of parameters.
I/O Pin Equivalent Schematic
CC
and Ground as indicated in
Pxn
“Alternate Port Functions” on page
C
pin
Figure
9-1. Refer to
“Electrical Characteristics(1)” on page
"General Digital I/O" for
See Figure
R
Details
pu
71. Refer to the individual
Logic
7734P–AVR–08/10