IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 99

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

3.22 ENCODER
3.22.1 LINE CODE RULE
3.22.1.1 T1/J1 Mode
be selected by the T_MD bit.
3.22.1.2 E1 Mode
selected by the T_MD bit.
3.22.2 BPV ERROR INSERTION
be transmitted by a transition from ‘0’ to ‘1’ on the BPV_INS bit.
3.22.3 ALL ‘ONE’S INSERTION
inserted automatically to the data stream to be transmitted by setting the
ATAO bit.
Table 58: Related Bit / Register In Chapter 3.22
Functional Description
IDT82P2288
BPV_INS
In T1/J1 mode, the B8ZS line code rule or the AMI line code rule can
In E1 mode, the HDB3 line code rule or the AMI line code rule can be
For test purpose, a BPV error can be inserted to the data stream to
When the LOS is detected in the receive path, all ‘One’s will be
T_MD
ATAO
Bit
Maintenance Function Control 2
Maintenance Function Control 1
Transmit Configuration 0
Register
02C, 12C, 22C, 32C,
42C, 52C, 62C, 72C
022, 122, 222, 322,
031, 131, 231, 331,
422, 522, 622, 722
431, 531, 631, 731
Address (Hex)
99
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.23 TRANSMIT JITTER ATTENUATOR
or not. This selection is made by the TJA_E bit.
Figure 7.
data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the TJA_DP[1:0]
bits. Accordingly, the constant delay produced by the Jitter Attenuator is
16 bits, 32 bits or 64 bits. The 128-bit FIFO is used when large jitter
tolerance is expected, and the 32-bit FIFO is used in delay sensitive
applications.
stored in the FIFO. The DPLL can only attenuate the incoming jitter
whose frequency is above Corner Frequency (CF). The jitter which
frequency is lower than the CF passes through the DPLL without any
attenuation. In T1/J1 applications, the CF of the DPLL can be 5 Hz or
1.26 Hz, as selected by the TJA_BW bit. In E1 applications, the CF of
the DPLL can be 6.77 Hz or 0.87 Hz, as selected by the TJA_BW bit.
The lower the CF is, the longer time is needed to achieve synchroniza-
tion.
will overflow. If the incoming data moves slower than the outgoing data,
the FIFO will underflow. The overflow or underflow is captured by the
TJA_IS bit. When the TJA_IS bit is ‘1’, an interrupt will be reported on
the INT pin if enabled by the TJA_IE bit.
enabled by setting the TJA_LIMT bit. When the JA-Limit function is
enabled, the speed of the outgoing data will be adjusted automatically if
the FIFO is close to its full or emptiness. The criteria of speed adjust-
ment start are listed in Table 6. Though the LA-Limit function can reduce
the possibility of FIFO overflow and underflow, the quality of jitter attenu-
ation is deteriorated.
read and write pointer of the FIFO or the peak-peak interval between the
read and write pointer of the FIFO can be indicated in the TJITT[6:0]
bits. When the TJITT_TEST bit is ‘0’, the current interval between the
read and write pointer of the FIFO will be written into the TJITT[6:0] bits.
When the TJITT_TEST bit is ‘1’, the current interval is compared with
the old one in the TJITT[6:0] bits and the larger one will be indicated by
the TJITT[6:0] bits.
G.703, G.736 - 739, G.823, G.824, ETSI 300011, ETSI TBR 12/13,
AT&T TR62411, TR43802, TR-TSY 009, TR-TSY 253, TR-TRY 499
standards. Refer to Chapter 7.10 Jitter Tolerance and Chapter 7.10
Jitter Tolerance for details.
The Transmit Jitter Attenuator of each link can be chosen to be used
The Jitter Attenuator consists of a FIFO and a DPLL, as shown in
The FIFO is used as a pool to buffer the jittered input data, then the
The DPLL is used to generate a de-jittered clock to clock out the data
If the incoming data moves faster than the outgoing data, the FIFO
To avoid overflowing or underflowing, the JA-Limit function can be
Selected by the TJITT_TEST bit, the real time interval between the
The performance of Receive Jitter Attenuator meets the ITUT I.431,
March 04, 2009