IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 152

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

T1/J1 Maintenance Function Control 1 (02CH, 12CH, 22CH, 32CH, 42CH, 52CH, 62CH, 72CH)
LAC:
RAISE:
ATAO:
Programming Information
IDT82P2288
Bit Name
This bit selects the LOS criterion.
= 0: The T1.231 is selected. In short haul application, the LOS is declared when the incoming signal level is less than 800 mVpp for 175 consecu-
tive bit intervals and is cleared when the incoming signal level is greater than 1 Vpp and has an average mark density of at least 12.5% and less
than 100 consecutive zeros in 128 consecutive bit periods. In long haul application, the LOS is declared when the incoming signal level is less than
Q dB below nominal (set in the LOS[4:0] bits (b4~0, T1/J1-029H,...)) for 175 consecutive bit intervals and is cleared when the incoming signal level
is greater than (Q + 4 dB) and has an average mark density of at least 12.5% and less than 100 consecutive zeros in 128 consecutive bit periods.
= 1: The I.431 is selected. In short haul application, the LOS is declared when the incoming signal level is less than 800 mVpp for 1544 consecutive
bit intervals and is cleared when the incoming signal level is greater than 1 Vpp and has an average mark density of at least 12.5% and less than
100 consecutive zeros in 128 consecutive bit periods. In long haul application, the LOS is declared when the incoming signal level is less than Q
dB below nominal (set in the LOS[4:0] bits (b4~0, T1/J1-029H,...)) for 1544 consecutive bit intervals and is cleared when the incoming signal level
is greater than (Q + 4 dB) and has an average mark density of at least 12.5% and less than 100 consecutive zeros in 128 consecutive bit periods.
This bit determines whether all ’One’s can be inserted in the receive path when the LOS is detected.
= 0: Disable the insertion.
= 1: Enable the insertion.
This bit determines whether all ’One’s can be inserted in the transmit path when the LOS is detected in the receive path.
= 0: Disable the insertion.
= 1: Enable the insertion.
Default
Bit No.
Type
7
6
Reserved
5
4
152
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3
LAC
R/W
2
0
RAISE
R/W
1
0
March 04, 2009
ATAO
R/W
0
0