IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 38

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

3.8.1.2 Error Event And Out Of Synchronization Detection
to monitor the received data stream to detect errors and judge if it is out
of synchronization.
Super Frame (SF) Format
bits, it is out of synchronization. Then if the REFEN bit is ‘1’, the Frame
Processor will start to search for synchronization again. If the REFEN bit
is ‘0’, no error can lead to reframe except for manually setting. The
manual reframe is executed by a transition from ‘0’ to ‘1’ on the REFR
bit. During out of synchronization state, the error event detection is
suspended.
previous one, the change of frame alignment event is generated. This
event is captured by the COFAI bit and is forwarded to the Performance
Monitor.
Extended Super Frame (ESF) Format
Table 15: The Structure of SLC-96 (Continued)
Functional Description
IDT82P2288
Frame No.
After the frame is in synchronization, the Frame Processor continues
In SF format, two kinds of errors are detected:
• Severely Ft Bit Error: Each received Ft bit is compared with the
• F Bit Error: Each received F bit is compared with the expected one
When the F Bit Error number exceeds the ratio set in the M2O[1:0]
Once resynchronized, if the new-found F bit position differs from the
In ESF format, four kinds of errors are detected:
• Frame Alignment Bit Error: Each received Frame Alignment bit is
• CRC-6 Error: When the local calculated CRC-6 of the current
59
61
63
65
67
69
71
expected one (refer to Table 12). Each unmatched Ft bit leads to
an Ft bit error event. When 2 or more Ft bit errors are detected in a
6-basic-frame fixed window, the severely Ft bit error occurs. This
error event is captured by the SFEI bit.
(refer to Table 12). Each unmatched F bit leads to an F bit error
event. This error event is captured by the FERI bit and is for-
warded to the Performance Monitor.
compared with the expected one (refer to Table 13). Each
unmatched bit leads to a frame alignment bit error event. This error
event is captured by the FERI bit and is forwarded to the Perfor-
mance Monitor.
received ESF frame does not match the received CRC-6 of the
F-Bit (Frame Alignment) - Ft
0
1
0
1
0
1
0
Data Bit
The Bit In Each Channel
1 - 8
1 - 8
1 - 8
1 - 8
1 - 8
1 - 8
1 - 8
Signaling Bit
-
-
-
-
-
-
-
38
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
the M2O[1:0] bits, it is out of synchronization. Then if the REFEN bit is
‘1’, the Frame Processor will start to search for synchronization again.
Additionally, the Excessive CRC-6 Error also leads to out of ESF
synchronization. In this condition, both the REFEN bit being ‘1’ and the
REFCRCE bit being ‘1’ will allow the Frame Processor to search for
synchronization again. If the REFEN bit is ‘0’, no error can lead to
reframe except for manually setting. The manual reframe is executed by
a transition from ‘0’ to ‘1’ on the REFR bit. During out of synchronization
state, the error event detection is suspended.
previous one, the change of frame alignment event is generated. This
event is captured by the COFAI bit and is forwarded to the Performance
Monitor.
T1 Digital Multiplexer (DM) Format (T1 only)
Frame No.
• Excessive CRC-6 Error: Once the accumulated CRC-6 errors
• Severely Frame Alignment Bit Error: When 2 or more frame align-
When the Frame Alignment Bit Error number exceeds the ratio set in
Once resynchronized, if the new-found F bit position differs from the
In T1 DM format, three kinds of errors are detected:
• Severely Ft Bit Error: Each received Ft bit is compared with the
• F Bit Error: Each received F bit is compared with the expected one
60
62
64
66
68
70
72
next received ESF frame, a single CRC-6 error event is generated.
This error event is captured by the BEEI bit and is forwarded to the
Performance Monitor.
exceed 319 occasions (> 319) in a 1 second fixed window, an
excessive CRC-6 error event is generated. This error event is cap-
tured by the EXCRCERI bit and is forwarded to the Performance
Monitor.
ment bit errors are detected in a 1-ESF-frame fixed window, the
severely frame alignment bit error occurs. This error event is cap-
tured by the SFEI bit.
expected one (refer to Table 14). Each unmatched Ft bit leads to
an Ft bit error event. When 2 or more Ft bit errors are detected in a
6-basic-frame fixed window, the severely Ft bit error occurs. This
error event is captured by the SFEI bit.
(refer to Table 14). Each unmatched F bit leads to an F bit error
F-Bit (Frame Alignment) - Fs
S1 (Switch Bit)
S2 (Switch Bit)
S3 (Switch Bit)
S4 (Switch Bit)
A2 (Alarm Bit)
1 (Spoiler Bit)
0
Data Bit
The Bit In Each Channel
1 - 7
1 - 8
1 - 8
1 - 7
1 - 8
1 - 8
1 - 7
March 04, 2009
Signaling Bit
B (bit 8)
C (bit 8)
D (bit 8)
-
-
-
-