IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 61

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

3.11 HDLC RECEIVER
selected position and processes the data according to the selected
mode.
3.11.1 HDLC CHANNEL CONFIGURATION
& #3) per link are provided for HDLC extraction from the received data
stream. In T1/J1 mode SF & SLC-96 formats, two HDLC Receivers (#2
& #3) per link are provided for HDLC extraction. In E1 mode, three
HDLC Receivers (#1, #2 & #3) per link are provided for HDLC extraction.
Except in T1/J1 mode ESF & T1 DM formats, the HDLC channel of
Table 29: Related Bit / Register In Chapter 3.11.1
3.11.2 HDLC MODE
Receiver selects the HDLC mode (per Q.921).
3.11.2.1 HDLC Mode
parts as shown in Figure 14. Each HDLC packet starts with a 7E (Hex)
opening flag and ends with the same flag. The closing flag may also
Functional Description
IDT82P2288
The HDLC Receiver extracts the HDLC data stream from the
In T1/J1 mode ESF & T1 DM formats, three HDLC Receivers (#1, #2
Setting the RHDLCM bit to ‘0’ (default) in the corresponding HDLC
The structure of a standard HDLC packet consists of the following
BITEN[7:0]
RDLEN3
RDLEN2
RDLEN1
'01111110'
TS[4:0]
EVEN
one byte
ODD
Bit
Flag
RHDLC1 Assignment (E1 only) / RHDLC2 Assignment /
RHDLC1 Bit Select (E1 only) / RHDLC2 Bit Select /
two bytes
FCS
RHDLC Enable Control
RHDLC3 Assignment
RHDLC3 Bit Select
Register
Figure 14. Standard HDLC Packet
Information
n bytes
b7
61
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
HDLC #1 is fixed in the DL bit (in ESF format) and D bit in CH24 (in T1
DM format) respectively (refer to Table 13 & Table 14), the other HDLC
channels are configured as follows:
the corresponding RDLEN bit is set to ‘1’.
serve as the opening flag of the next HDLC packet. Following the
opening flag, two-byte address is compared if the address comparison
mode is selected. Before the closing flag, two bytes of CRC-CCITT
frame check sequences (FCS) are provided to check all the HDLC
packet (excluding the opening flag and closing flag).
• Set the EVEN bit and/or the ODD bit to select the even and/or odd
• Set the TS[4:0] bits to define the channel/timeslot of the assigned
• Set the BITEN[7:0] bits to select the bits of the assigned channel/
Then all the functions of the HDLC Receiver will be enabled only if
390, 490, 590, 690, 790 / 091, 191, 291, 391, 491, 591, 691, 791
28D, 38D, 48D, 58D, 68D, 78D / 08E, 18E, 28E, 38E, 48E, 58E,
08F, 18F, 28F, 38F, 48F, 58F, 68F, 78F (E1 only) / 090, 190, 290,
08C, 18C, 28C, 38C, 48C, 58C, 68C, 78C (E1 only) / 08D, 18D,
frames;
frame;
timeslot.
one byte
Control
08B, 18B, 28B, 38B, 48B, 58B, 68B, 78B
one byte
low byte
address
b0
(optional)
Address
b7
Address (Hex)
68E, 78E
high byte
one byte
address
'01111110'
one byte
Flag
March 04, 2009
C/R
b0