IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 95

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

3.20.2 HDLC TRANSMITTER
form HDLC packet data stream.
3.20.2.1 HDLC Channel Configuration
#2 & #3) per link are provided for HDLC insertion to the data stream to
be transmitted. In T1/J1 mode SF & SLC-96 formats, two HDLC Trans-
mitters (#2 & #3) per link are provided for HDLC insertion. In E1 mode,
three HDLC Transmitters (#1, #2 & #3) per link are provided for HDLC
insertion. Except in T1/J1 mode ESF & T1 DM formats, the HDLC
channel of HDLC Transmitter #1 is fixed in the DL bit (in ESF format)
and D bit in CH24 (in T1 DM format) respectively (refer to Table 13 &
Table 14), the other HDLC channel is configured as the follows:
the corresponding TDLEN bit is set to ‘1’.
Table 52: Related Bit / Register In Chapter 3.20.2.2 ~ Chapter 3.20.2.4
Functional Description
IDT82P2288
The HDLC Transmitter inserts the data into the selected position to
In T1/J1 mode ESF & T1 DM formats, three HDLC Transmitters (#1,
• Set the EVEN bit and/or the ODD bit to select the even and/or odd
• Set the TS[4:0] bits to define the channel/timeslot of the assigned
• Set the BITEN[7:0] bits to select the bits of the assigned channel/
Then all the functions of the HDLC Transmitter will be enabled only if
frames;
frame;
timeslot.
UDRUNE
THDLCM
DAT[7:0]
UDRUNI
TDLEN3
TDLEN2
TDLEN1
ABORT
HL[1:0]
LL[1:0]
RDYE
TRST
RDYI
EOM
EMP
RDY
FUL
Bit
TFIFO1 Threshold / TFIFO2 Threshold / TFIFO3 Threshold
THDLC1 Interrupt Indication / THDLC2 Interrupt Indication /
THDLC1 Interrupt Control / THDLC2 Interrupt Control /
THDLC1 Control / THDLC2 Control / THDLC3 Control
TFIFO1 Status / TFIFO2 Status / TFIFO3 Status
THDLC1 Data / THDLC2 Data / THDLC3 Data
THDLC3 Interrupt Indication
THDLC3 Interrupt Control
THDLC Enable Control
Register
95
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 51: Related Bit / Register In Chapter 3.20.2.1
3.20.2.2 HDLC Mode
selects the HDLC mode (per Q.921).
BITEN[7:0]
TDLEN3
TDLEN2
TDLEN1
TS[4:0]
Setting the THDLCM bit to ‘0’ (default) in the HDLC Transmitter
EVEN
ODD
Bit
0A7, 1A7, 2A7, 3A7, 4A7, 5A7, 6A7, 7A7 / 0A8, 1A8, 2A8, 3A8, 4A8,
0B0, 1B0, 2B0, 3B0, 4B0, 5B0, 6B0, 7B0 / 0B1, 1B1, 2B1, 3B1, 4B1,
0B6, 1B6, 2B6, 3B6, 4B6, 5B6, 6B6, 7B6 / 0B7, 1B7, 2B7, 3B7, 4B7,
0B3, 1B3, 2B3, 3B3, 4B3, 5B3, 6B3, 7B3 / 0B4, 1B4, 2B4, 3B4, 4B4,
0AD, 1AD, 2AD, 3AD, 4AD, 5AD, 6AD, 7AD / 0AE, 1AE, 2AE, 3AE,
4AB, 5AB, 6AB, 7AB / 0AC, 1AC, 2AC, 3AC, 4AC, 5AC, 6AC, 7AC
0AA, 1AA, 2AA, 3AA, 4AA, 5AA, 6AA, 7AA / 0AB, 1AB, 2AB, 3AB,
4AE, 5AE, 6AE, 7AE / 0AF, 1AF, 2AF, 3AF, 4AF, 5AF, 6AF, 7AF
5A8, 6A8, 7A8 / 0A9, 1A9, 2A9, 3A9, 4A9, 5A9, 6A9, 7A9
5B1, 6B1, 7B1 / 0B2, 1B2, 2B2, 3B2, 4B2, 5B2, 6B2, 7B2
5B7, 6B7, 7B7 / 0B8, 1B8, 2B8, 3B8, 4B8, 5B8, 6B8, 7B8
5B4, 6B4, 7B4 / 0B5, 1B5, 2B5, 3B5, 4B5, 5B5, 6B5, 7B5
only) / THDLC2 Bit Select /
THDLC1 Assignment (E1
only) / THDLC2 Assign-
ment / THDLC3 Assign-
THDLC1 Bit Select (E1
THDLC Enable Control
THDLC3 Bit Select
084, 184, 284, 384, 484, 584, 684, 784
Register
ment
Address (Hex)
08A, 18A, 28A, 38A, 48A, 58A,
286, 386, 486, 586, 686, 786 /
289, 389, 489, 589, 689, 789 /
685, 785 (E1 only) / 086, 186,
688, 788 (E1 only) / 089, 189,
085, 185, 285, 385, 485, 585,
087, 187, 287, 387, 487, 587,
088, 188, 288, 388, 488, 588,
084, 184, 284, 384, 484, 584,
Address (Hex)
68A, 78A
687, 787
684, 784
March 04, 2009