IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 69

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

Table 36: A-Law Digital Milliwatt Pattern
Table 37: µ-Law Digital Milliwatt Pattern
Functional Description
IDT82P2288
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
The following methods can be executed on the signaling bits to be
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Bit 0
Bit 0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 1
Bit 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 2
Bit 2
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Bit 3
Bit 3
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
Bit 4
Bit 4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit 5
Bit 5
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
Bit 6
Bit 6
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit 7
Bit 7
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
69
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
output on the RSIGn/MRSIGA(MRSIGB) pins on a per-channel/per-TS
basis or on a global basis of the corresponding link (the methods are
arranged from the highest to the lowest in priority):
by specifying the address in the ADDRESS[6:0] bits. Whether the data is
read from or written into the specified indirect register is determined by
the RWN bit and the data is in the D[7:0] bits. The access status is indi-
cated in the BUSY bit. Refer to Chapter 4.5 Indirect Register Access
Scheme for details about the indirect registers write/read access.
• Selected by the ABXX bit, the signaling bits can be valid in the
• Enabled by the SIGSNAP bit, the signaling snapshot will be exe-
• Enabled by the GSTRKEN bit, the signaling bits (ABCD) of all
The indirect registers of the Receive Payload Control are accessed
upper 2-bit positions of the lower nibble of each channel or in the
lower nibble of each channel. The other bits of the channel are
Don’t Care conditions. This function is only supported in T1/J1
mode ESF/SLC-96 format.
cuted. The signaling snapshot means that the signaling bits of the
first basic frame are locked and output as the signaling bits of the
current whole multi-frame. This function is not supported in T1 DM
format.
channels/timeslots of the corresponding link will be replaced by the
signaling trunk conditioning code in the A,B,C,D bits. When the
GSTRKEN bit is ‘0’, the replacement will be performed on a per-
channel/per-TS basis by setting the STRKEN bit in the corre-
sponding channel/timeslot.
March 04, 2009