IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 223

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

T1/J1 RPLC Access Data (0CFH, 1CFH, 2CFH, 3CFH, 4CFH, 5CFH, 6CFH, 7CFH)
D[7:0]:
If data is to be written into the indirect register, this register must be written before the target indirect register’s address and RWN=0 is written into the
RPLC Access Control register. If data is to be read from the indirect register, the target indirect register’s address and RWN=1 must be written into the
RPLC Access Control register first, then this register will contain the requested data byte.
T1/J1 RPLC Configuration (0D0H, 1D0H, 2D0H, 3D0H, 4D0H, 5D0H, 6D0H, 7D0H)
SIGSNAP:
GSTRKEN:
GSUBST[2:0]:
Programming Information
IDT82P2288
GSUBST[2:0]
Bit Name
Bit Name
This register holds the value which will be read from or written into the indirect registers (from 01H to 18H & from 21H to 38H & from 41H to 58H).
This bit is valid when SF, ESF or SLC-96 frame is in synchronization.
= 0: Disable the signaling snapshot.
= 1: Enable the signaling snapshot. That is, the signaling bits of the first frame are locked and output on the RSIGn/MRSIGA(MRSIGB) pin as the
signaling bits of the current whole SF, ESF or SLC-96 frame.
= 0: The replacement is performed on a per-channel basis by setting the STRKEN bit (b4, T1/J1-ID-41~58H) in the corresponding channel.
= 1: The signaling bits (ABCD) of all channels are replaced by the signaling trunk conditioning code in the A,B,C,D bits (b3~0, T1/J1-ID-41~58H).
These bits select the replacement of all the channels.
Default
Default
Bit No.
Bit No.
Type
Type
others
000
001
010
011
The replacement is performed on a per-channel basis by setting the SUBST[2:0] bits (b7~5, T1/J1-ID-01~18H) in the corresponding channel.
The data of all channels is replaced by the data trunk code set in the DTRK[7:0] bits (b7~0, T1/J1-ID-21~38H).
The data of all channels is replaced by the A-Law digital milliwatt pattern.
The data of all channels is replaced by the µ-Law digital milliwatt pattern.
Reserved.
SIGSNAP
R/W
R/W
D7
7
0
7
1
GSTRKEN
R/W
R/W
D6
6
0
6
0
R/W
D5
5
0
5
Reserved
R/W
D4
4
0
4
Replacement Selection
223
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
R/W
D3
3
0
3
GSUBST2
R/W
R/W
D2
2
0
2
0
GSUBST1
R/W
R/W
D1
1
0
1
0
March 04, 2009
GSUBST0
R/W
R/W
D0
0
0
0
0