IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 7

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

List of Tables
Table 1: Operating Mode Selection ........................................................................................................................................................................... 23
Table 2: Related Bit / Register In Chapter 3.1 ........................................................................................................................................................... 23
Table 3: Impedance Matching Value For The Receiver ............................................................................................................................................. 24
Table 4: Related Bit / Register In Chapter 3.2 ........................................................................................................................................................... 26
Table 5: Related Bit / Register In Chapter 3.3 & Chapter 3.4 .................................................................................................................................... 27
Table 6: Criteria Of Speed Adjustment Start .............................................................................................................................................................. 28
Table 7: Related Bit / Register In Chapter 3.6 ........................................................................................................................................................... 28
Table 8: Excessive Zero Error Definition ................................................................................................................................................................... 30
Table 9: LOS Condition In T1/J1 Mode ...................................................................................................................................................................... 32
Table 10: LOS Condition In E1 Mode .......................................................................................................................................................................... 32
Table 11: Related Bit / Register In Chapter 3.7 ........................................................................................................................................................... 33
Table 12: The Structure of SF ..................................................................................................................................................................................... 34
Table 13: The Structure of ESF ................................................................................................................................................................................... 35
Table 14: The Structure of T1 DM ............................................................................................................................................................................... 36
Table 15: The Structure of SLC-96 .............................................................................................................................................................................. 37
Table 16: Interrupt Source In T1/J1 Frame Processor ................................................................................................................................................ 40
Table 17: Related Bit / Register In Chapter 3.8.1 ........................................................................................................................................................ 40
Table 18: The Structure Of TS0 In CRC Multi-Frame .................................................................................................................................................. 45
Table 19: FAS/NFAS Bit/Pattern Error Criteria ............................................................................................................................................................ 47
Table 20: Interrupt Source In E1 Frame Processor ..................................................................................................................................................... 49
Table 21: Related Bit / Register In Chapter 3.8.2 ........................................................................................................................................................ 50
Table 22: Monitored Events In T1/J1 Mode ................................................................................................................................................................. 54
Table 23: Related Bit / Register In Chapter 3.9.1 ........................................................................................................................................................ 55
Table 24: Monitored Events In E1 Mode ..................................................................................................................................................................... 56
Table 25: Related Bit / Register In Chapter 3.9.2 ........................................................................................................................................................ 57
Table 26: RED Alarm, Yellow Alarm & Blue Alarm Criteria ......................................................................................................................................... 58
Table 27: Related Bit / Register In Chapter 3.10.1 ...................................................................................................................................................... 59
Table 28: Related Bit / Register In Chapter 3.10.2 ...................................................................................................................................................... 60
Table 29: Related Bit / Register In Chapter 3.11.1 ...................................................................................................................................................... 61
Table 30: Interrupt Summarize In HDLC Mode ........................................................................................................................................................... 63
Table 31: Related Bit / Register In Chapter 3.11.2 ...................................................................................................................................................... 63
Table 32: Related Bit / Register In Chapter 3.12 ......................................................................................................................................................... 64
Table 33: Related Bit / Register In Chapter 3.13 ......................................................................................................................................................... 64
Table 34: Related Bit / Register In Chapter 3.14 ......................................................................................................................................................... 65
Table 35: Related Bit / Register In Chapter 3.15 ......................................................................................................................................................... 67
Table 36: A-Law Digital Milliwatt Pattern ..................................................................................................................................................................... 69
Table 37: µ-Law Digital Milliwatt Pattern ..................................................................................................................................................................... 69
Table 38: Related Bit / Register In Chapter 3.16 ......................................................................................................................................................... 70
Table 39: Operating Modes Selection In T1/J1 Receive Path ..................................................................................................................................... 71
Table 40: Operating Modes Selection In E1 Receive Path .......................................................................................................................................... 77
Table 41: Related Bit / Register In Chapter 3.17 ......................................................................................................................................................... 79
Table 42: Operating Modes Selection In T1/J1 Transmit Path .................................................................................................................................... 80
Table 43: Operating Modes Selection In E1 Transmit Path ......................................................................................................................................... 86
Table 44: Related Bit / Register In Chapter 3.18 ......................................................................................................................................................... 88
Table 45: Related Bit / Register In Chapter 3.19 ......................................................................................................................................................... 89
Table 46: Related Bit / Register In Chapter 3.20.1.1 ................................................................................................................................................... 91
Table 47: E1 Frame Generation .................................................................................................................................................................................. 92
Table 48: Control Over E Bits ...................................................................................................................................................................................... 92
March 04, 2009
List of Tables
7