IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 265

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

E1 TBIF Operating Mode (043H, 143H, 243H, 343H, 443H, 543H, 643H, 743H)
TMODE:
E1 TBIF TS Offset (044H, 144H, 244H, 344H, 444H, 544H, 644H, 744H)
TSOFF[6:0]:
start of the corresponding frame input on the TSDn/MTSDA(MTSDB) pin. The signaling bits on the TSIGn/MTSIGA(MTSIGB) pin are always per-
timeslot aligned with the data on the TSDn/MTSDA(MTSDB) pin.
can be configured from 0 to 127 timeslots (0 & 127 are included).
E1 TBIF Bit Offset (045H, 145H, 245H, 345H, 445H, 545H, 645H, 745H)
EDGE:
BOFF[2:0]:
corresponding frame input on the TSDn/MTSDA(MTSDB) pin. The signaling bits on the TSIGn/MTSIGA(MTSIGB) pin are always per-timeslot aligned
with the data on the TSDn/MTSDA(MTSDB) pin.
Programming Information
IDT82P2288
Bit Name
Bit Name
Bit Name
In Transmit Non-multiplexed mode, this bit selects the sub-mode.
= 0: The Transmit System Interface is operated in Transmit Clock Master mode. The timing signal for clocking the data and the framing pulse to
align the data input on the TSDn pin are provided from the processed data from the device.
= 1: The Transmit System Interface is operated in Transmit Clock Slave mode. The timing signal for clocking the data and the framing pulse to align
the data input on the TSDn pin are provided by the system side.
These bits give a binary number to define the timeslot offset. The timeslot offset is between the framing pulse on the TSFSn/MTSFS pin and the
In Non-multiplexed mode, the timeslot offset can be configured from 0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the timeslot offset
This bit is valid when the CMS bit (b2, E1-042H,...) is ‘1’.
= 0: The first active edge of TSCKn/MTSCK is selected to sample the data on the TSDn/MTSDA(MTSDB) and TSIGn/MTSIGA(MTSIGB) pins.
= 1: The second active edge of TSCKn/MTSCK is selected to sample the data on the TSDn/MTSDA(MTSDB) and TSIGn/MTSIGA(MTSIGB) pins.
These bits give a binary number to define the bit offset. The bit offset is between the framing pulse on the TSFSn/MTSFS pin and the start of the
Default
Default
Default
Bit No.
Bit No.
Bit No.
Type
Type
Type
Reserved
7
7
7
TSOFF6
R/W
6
6
0
6
Reserved
TSOFF5
R/W
5
5
0
5
TSOFF4
Reserved
R/W
4
4
0
4
265
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
TSOFF3
EDGE
R/W
R/W
3
3
0
3
0
TSOFF2
BOFF2
R/W
R/W
2
2
0
2
0
TSOFF1
BOFF1
R/W
R/W
1
1
0
1
0
March 04, 2009
TSOFF0
TMODE
BOFF0
R/W
R/W
R/W
0
1
0
0
0
0