IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 268
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IDT82P2288BB
Manufacturer Part Number
IDT82P2288BB
Description
TXRX T1/J1/E1 8CHAN 256-PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Type
Transceiverr
Datasheet
1.IDT82P2288BB.pdf
(362 pages)
Specifications of IDT82P2288BB
Protocol
IEEE 1149.1
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
256-PBGA
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Drivers/receivers
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
82P2288BB
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E1 RBIF Bit Offset (04AH, 14AH, 24AH, 34AH, 44AH, 54AH, 64AH, 74AH)
EDGE:
BOFF[2:0]:
are set to TS1 and TS16 overhead indication, the bit offset is supported in all the other conditions.
corresponding frame output on the RSDn/MRSDA(MRSDB) pin. The signaling bits on the RSIGn/MRSIGA(MRSIGB) pin are always per-channel
aligned with the data on the RSDn/MRSDA(MRSDB) pin.
E1 RTSFS Change Indication (04BH, 14BH, 24BH, 34BH, 44BH, 54BH, 64BH, 74BH)
RCOFAI:
TCOFAI:
Programming Information
IDT82P2288
Bit Name
Bit Name
This bit is valid when the CMS bit (b1, E1-046H,...) is ‘1’.
= 0: The first active edge of RSCKn/MRSCK is selected to update the data on the RSDn/MRSDA(MRSDB) and RSIGn/MRSIGA(MRSIGB) pins.
= 1: The second active edge of RSCKn/MRSCK is selected to update the data on the RSDn/MRSDA(MRSDB) and RSIGn/MRSIGA(MRSIGB)
pins.
Except that in the Receive Master mode, when the OHD bit (b3, E1-048H,...), the SMFS bit (b2, E1-048H,...) and the CMFS bit (b1, E1-048H,...)
These bits give a binary number to define the bit offset. The bit offset is between the framing pulse on the RSFSn/MRSFS pin and the start of the
This bit is valid in Receive Clock Slave mode and Receive Multiplexed mode.
= 0: The interval of the pulses on the RSFSn/MRSFS pin is an integer multiple of 125 µs.
= 1: The interval of the pulses on the RSFSn/MRSFS pin is not an integer multiple of 125 µs.
This bit will be cleared if a ’1’ is written to it.
This bit is valid in Transmit Clock Slave mode and Transmit Multiplexed mode.
= 0: The pulse on the TSFSn/MTSFS pin is an integer multiple of 125 µs.
= 1: The pulse on the TSFSn/MTSFS pin is not an integer multiple of 125 µs.
This bit will be cleared if a ’1’ is written to it.
Default
Default
Bit No.
Bit No.
Type
Type
7
7
6
6
Reserved
5
5
Reserved
4
4
268
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
EDGE
R/W
3
0
3
BOFF2
R/W
2
0
2
RCOFAI
BOFF1
R/W
R
1
0
1
0
March 04, 2009
TCOFAI
BOFF0
R/W
R
0
0
0
0
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