IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 339

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

6
ACCESS PORT
as described in the IEEE 1149.1 standards.
registers plus a Test Access Port (TAP) controller. Control of the TAP is
achieved through signals applied to the Test Mode Select (TMS) and
6.1
ISTER (IR)
select the test to be executed or the data register to be accessed or
both.
IEEE STD 1149.1 JTAG Test Access Port
IDT82P2288
The IDT82P2288 supports the digital Boundary Scan Specification
The boundary scan architecture consists of data and instruction
The IR (Instruction Register) with instruction decode block is used to
IEEE STD 1149.1 JTAG TEST
JTAG INSTRUCTIONS AND INSTRUCTION REG-
TRST
TMS
TCK
TDI
(Test Access Port)
Controller
TAP
DIR (Device Identification Register)
BSR (Boundary Scan Register)
IR (Instruction Register)
BR (Bypass Register)
Figure 41. JTAG Architecture
Control<6:0>
339
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Test Clock (TCK) input pins. Data is shifted into the registers via the Test
Data Input (TDI) pin, and shifted out of the registers via the Test Data
Output (TDO) pin. Both TDI and TDO are clocked at a rate determined
by TCK.
Register), DIR (Device Identification Register), BR (Bypass Register)
and IR (Instruction Register). These will be described in the following
pages. Refer to Figure - 41 for architecture.
Table 82 for details of the codes and the instructions related.
The JTAG boundary scan registers include BSR (Boundary Scan
The instructions are shifted in LSB first to this 3-bit register. See
Output Enable
Select
MUX
March 04, 2009
TDO