IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 243

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

E1 Transmit Jitter Attenuation Configuration (021H, 121H, 221H, 321H, 421H, 521H, 621H, 721H)
TJITT_TEST:
TJA_LIMT:
of the JA can be widened to track the short term input jitter, thereby avoiding data corruption. This bit selects whether the bandwidth is normal or
widened.
TJA_E:
TJA_DP[1:0]:
TJA_BW:
Programming Information
IDT82P2288
= 0: The real time interval between the read and write pointer of the FIFO is indicated in the TJITT[6:0] bits (b6~0, E1-038H,...). That is, the current
interval between the read and write pointer of the FIFO will be written into the TJITT[6:0] bits (b6~0, E1-038H,...).
= 1: The peak-peak interval between the read and write pointer of the FIFO is indicated in the TJITT[6:0] bits (b6~0, E1-038H,...). That is, the
current interval is compared with the old one in the TJITT[6:0] bits (b6~0, E1-038H,...) and the larger one will be indicated by the TJITT[6:0] bits
(b6~0, E1-038H,...); otherwise, the value in the TJITT[6:0] bits (b6~0, E1-038H,...) is not changed.
When the read and write pointer of the FIFO are within 2/3/4 bits (corresponding to the FIFO depth) of overflowing or underflowing, the bandwidth
= 0: Normal bandwidth is selected.
= 1: Widen bandwidth is selected. In this case, the JA will not attenuate the input jitter until the read/write pointer’s position is outside the 2/3/4 bits
window.
= 0: Disable the Transmit Jitter Attenuator.
= 1: Enable the Transmit Jitter Attenuator.
These two bits select the Jitter Attenuation Depth.
= 00: The Jitter Attenuation Depth is 128-bit.
= 01: The Jitter Attenuation Depth is 64-bit.
= 10 / 11: The Jitter Attenuation Depth is 32-bit.
This bit select the Jitter Transfer Function Bandwidth.
= 0: 6.77 Hz.
= 1: 0.87 Hz.
Bit Name
Default
Bit No.
Type
7
Reserved
6
TJITT_TEST
R/W
5
0
TJA_LIMT
R/W
243
4
0
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
TJA_E
R/W
3
0
TJA_DP1
R/W
2
0
TJA_DP0
R/W
1
0
March 04, 2009
TJA_BW
R/W
0
0