IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 86

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

3.18.2 E1 MODE
plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
TSDn pin is used to input the data to each link at the bit rate of 2.048
Mb/s. While in the Multiplexed Mode, the data is byte interleaved from
two high speed data streams and inputs on the MTSDA1 (MTSDB1) and
MTSDA2 (MTSDB2) pins at the bit rate of 8.192 Mb/s.
transmit system interface is in Transmit Clock Slave mode, otherwise if
the device outputs clock TSCK from itself, the transmit system interface
is in Transmit Clock Master mode.
Table 43: Operating Modes Selection In E1 Transmit Path
Functional Description
IDT82P2288
NOTE:
1. When the G56K, GAP bits in TPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. In Transmit Multiplexed mode, two sets of multiplexed data and signaling pins (A and B) are provided corresponding to two multiplexed buses. Their functions are the same. One is the
backup for the other. One set is selected by the MTSDA bit when used.
TMUX
In E1 mode, the Transmit System Interface can be set in Non-multi-
In the Non-multiplexed mode, if the TSCK is from outside, the
0
1
TMODE
X
0
1
not both 0s
G56K, GAP
00
X
X
1
Transmit Clock Master Full E1
Transmit Clock Master Fractional E1
Transmit Clock Slave
Transmit Multiplexed
Operating Mode
86
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
the entire E1 frame, the Transmit System Interface is in Transmit Clock
Master Full E1 mode. If only the clocks aligned to the selected timeslots
are output on TSCKn, the Transmit System Interface is in Transmit
Clock Master Fractional E1 mode.
each link into various operating modes and the pins’ direction of the
transmit system interface in different operating modes.
In the Transmit Clock Master mode, if TSCKn outputs pulses during
Table 43 summarizes how to set the transmit system interface of
MTSCK, MTSFS, MTSDA[1:2],
TSCKn, TSFSn, TSDn, TSIGn
MTSIGA[1:2] (MTSDB[1:2],
MTSIGB[1:2])
TSDn, TSIGn
Input
Transmit System Interface Pin
2
TSCKn, TSFSn
March 04, 2009
Output
X
X