IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 181

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

T1/J1 Mode (062H, 162H, 262H, 362H, 462H, 562H, 662H, 762H)
FDLBYP:
CRCBYP:
FDIS:
T1/J1 XDL0 (065H, 165H, 265H, 365H, 465H, 565H, 665H, 765H)
C[8:1]:
FDLBYP bit (b2, T1/J1-062H,...) are both ‘0’s. They contain the data to replace the Concentrator (C) bit. The C[1] is the LSB and it is transmitted first.
Programming Information
IDT82P2288
Bit Name
Bit Name
In ESF format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
= 0: Enable the DL bit position to be replaced by the Bit-Oriented Code, the Automatic Performance Report Message, the HDLC data or the idle
code (‘FFFF’ for T1 / ‘FF7E’ for J1).
= 1: Disable the DL bit position to be replaced by the above codes.
In T1 DM format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
= 0: The ‘D’ bit in Bit 6 of each Channel 24 is replaced with the HDLC data.
= 1: Disable the D bit position to be replaced by the HDLC data.
In SLC-96 format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
= 0: The Concentrator (C) bit, the Maintenance (M) bit, the Alarm (A) bit and the Switch (S) bit are replaced by the contents in the C[11:1] bits
(b2~0, T1/J1-066H,... & b7~0, T1/J1-065H,...), the M[3:1] bits (b5~3, T1/J1-066H,...), the A[2:1] bits (b1~0, T1/J1-067H,...) and the S[4:1] bits
(b5~2, T1/J1-067H,...) respectively.
= 1: Disable the Concentrator (C) bit, the Maintenance (M) bit, the Alarm (A) bit and the Switch (S) bit replacement.
This bit is valid in ESF format when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
= 0: The calculated 6-bit CRC of the previous ESF frame is inserted in the current CRC-bit positions in every 4th frame starting with Frame 2 of the
current ESF frame.
= 1: Disable the CRC-6 insertion.
= 0: Enable the generation of the SF / ESF / T1 DM / SLC-96 frame.
= 1: Disable the generation of the SF / ESF / T1 DM / SLC-96 frame.
These bits, together with the C[11:9] bits (b2~0, T1/J1-066H,...), are valid in SLC-96 format when the FDIS bit (b0, T1/J1-062H,...) and the
Default
Default
Bit No.
Bit No.
Type
Type
C8
R
7
7
0
C7
R
6
6
0
Reserved
C6
R
5
5
0
C5
R
4
4
0
181
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
C4
R
3
3
0
FDLBYP
R/W
C3
R
2
0
2
0
CRCBYP
R/W
C2
R
1
0
1
0
March 04, 2009
FDIS
R/W
C1
R
0
0
0
0