IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 56

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

3.9.2
performance monitoring. The overflow of each counter is reflected by an
Overflow Indication Bit, and can trigger an interrupt if the corresponding
Overflow Interrupt Enable Bit is set. This is shown in Table 24.
Table 24: Monitored Events In E1 Mode
Functional Description
IDT82P2288
Bipolar Violation (BPV) Error (in AMI decoding) or HDB3 Code Violation (CV) Error (in HDB3 decod-
ing)
FAS/NFAS Bit/Pattern Error
CRC-4 Error
Far End Block Error
The the new-found Basic frame alignment pattern position differs from the previous one
Out of Basic frame synchronization
PRGD Bit Error
NT FEBE Error
NT CRC Error
Several internal counters are used to count different events for
The internal counters can be updated in two ways:
• Auto-Update: Content in the internal counters is transfered to indi-
rect registers every one second automatically if the AUTOUPD bit
is ‘1’;
E1 MODE
Event
56
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
a new round of counting. No error event is lost during the update.
ADDR[3:0] bits. The LINKSEL[2:0] bits select the link and the ADDR[3:0]
bits select the specific PMON indirect register. Data read from the indi-
rect register is held in the DAT[7:0] bits.
• Manual-Update: Content in the internal counters is transfered to
All the internal counters will be resetted after the update and will start
The indirect registers are addressed by the LINKSEL[2:0] and
indirect registers when there is a transition from ‘0’ to ‘1’ on the
UPDAT bit, no matter whether the AUTOUPD bit is ‘1’ or ‘0’.
PRGD[15:0]
TCRCE[9:0]
TFEBE[9:0]
CRCE[9:0]
COFA[2:0]
FEBE[9:0]
LCV[15:0]
FER[11:0]
OOF[4:0]
Counter
Indication Bit
TFEBEOVI
PRGDOVI
COFAOVI
TCRCOVI
Overflow
FEBEOVI
Interrupt
CRCOVI
OOFOVI
FEROVI
LCVOVI
Interrupt Enable
March 04, 2009
TFEBEOVE
PRGDOVE
COFAOVE
TCRCOVE
FEBEOVE
Overflow
OOFOVE
CRCOVE
LCVOVE
FEROVE
Bit