IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 117

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

4.5
Payload Control blocks, per-channel/per-timeslot indirect register is
accessed by using an indirect register access scheme.
4.5.1
Table 81: Related Bit / Register In Chapter 4
Operation
IDT82P2288
In Receive CAS/RBS Buffer, Receive Payload Control and Transmit
The indirect register read access is as follows:
• Read the BUSY bit in the Access Status register to confirm the bit
• Write the Access Control register to initiate the read operation and
• Read the BUSY bit in the Access Status register again to confirm
ADDRESS[6:0]
is ‘0’;
specify the indirect register address;
the bit is ‘0’;
TEMODE
FM[1:0]
R_OFF
T_OFF
BUSY
D[7:0]
INDIRECT REGISTER ACCESS SCHEME
INDIRECT REGISTER READ ACCESS
T1/J1
RWN
Bit
-
TPLC Access Status / RPLC Access Status / RCRB Access Status
TPLC Access Data / RPLC Access Data / RCRB Access Data
TPLC Access Control / RPLC Access Control
Transmit Configuration 0
Receive Configuration 0
/ RCRB Access Control
T1/J1 Or E1 Mode
Software Reset
Register
117
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
4.5.2
• Read the indirect register data from the Access Data register.
An indirect register access request is completed within 4 µs.
The indirect register write access is as follows:
• Read the BUSY bit in the Access Status register to confirm the bit
• Write the Access Data register;
• Write the Access Control register to initiate the write operation and
An indirect register access request is completed within 4 µs.
is ‘0’;
specify the indirect register address.
INDIRECT REGISTER WRITE ACCESS
0C9, 1C9, 2C9, 3C9, 4C9, 5C9, 6C9, 7C9 / 0CE, 1CE, 2CE, 3CE,
4CE, 5CE, 6CE, 7CE / 0D4, 1D4, 2D4, 3D4, 4D4, 5D4, 6D4, 7D4
3CF, 4CF, 5CF, 6CF, 7CF / 0D5, 1D5, 2D5, 3D5, 4D5, 5D5, 6D5,
3CD, 4CD, 5CD, 6CD, 7CD / 0D3, 1D3, 2D3, 3D3, 4D3, 5D3,
0CA, 1CA, 2CA, 3CA, 4CA, 5CA, 6CA, 7CA / 0CF, 1CF, 2CF,
0C8, 1C8, 2C8, 3C8, 4C8, 5C8, 6C8, 7C8 / 0CD, 1CD, 2CD,
020, 120, 220, 320, 420, 520, 620, 720
028, 128, 228, 328, 428, 528, 628, 728
022, 122, 222, 322, 422, 522, 622, 722
Address (Hex)
6D3, 7D3
7D5
004
March 04, 2009