EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 78

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

5–16
Figure 5–8. clkena Implementation: Output Enable
PLLs in Cyclone IV Devices
Cyclone IV Device Handbook, Volume 1
clkin
clkena
clk_out
f
1
1
The clkena circuitry controlling the output C0 of the PLL to an output pin is
implemented with two registers instead of a single register, as shown in
Figure 5–8
signal is sampled on the falling edge of the clock (clkin).
This feature is useful for applications that require low power or sleep mode.
The clkena signal can also disable clock outputs if the system is not tolerant to
frequency overshoot during PLL resynchronization.
Altera recommends using the clkena signals when switching the clock source to the
PLLs or the GCLK. The recommended sequence is:
1. Disable the primary output clock by de-asserting the clkena signal.
2. Switch to the secondary clock using the dynamic select signals of the clock control
3. Allow some clock cycles of the secondary clock to pass before reasserting the
Cyclone IV GX devices offer two variations of PLLs: general purpose PLLs and
multipurpose PLLs. Cyclone IV E devices only have the general purpose PLLs.
The general purpose PLLs are used for general-purpose applications in the FPGA
fabric and periphery such as external memory interfaces. The multipurpose PLLs are
used for clocking the transceiver blocks. When the multipurpose PLLs are not used
for transceiver clocking, they can be used for general-purpose clocking.
For more details about the multipurpose PLLs used for transceiver clocking, refer to
the
block.
clkena signal. The exact number of clock cycles you must wait before enabling
the secondary clock is design-dependent. You can build custom logic to ensure
glitch-free transition when switching between different clock sources.
Cyclone IV Transceivers
shows the waveform example for a clock output enable. The clkena
chapter.
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
© December 2010 Altera Corporation
PLLs in Cyclone IV Devices
Figure
5–7.