EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 208

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

8–42
Cyclone IV Device Handbook, Volume 1
f
Figure 8–21
receiving the same configuration data. Configuration pins (nCONFIG, nSTATUS,
DCLK, DATA[7..0], and CONF_DONE) are connected to every device in the chain.
Configuration signals may require buffering to ensure signal integrity and prevent
clock skew problems. Ensure that the DCLK and DATA lines are buffered. Devices must
be of the same density and package. All devices start and complete configuration at
the same time.
Figure 8–21. Multi-Device FPP Configuration Using an External Host When Both Devices Receive the
Same Data
Notes to
(1) You must connect the pull-up resistor to a supply that provides an acceptable input signal for all devices in the chain.
(2) The nCEO pins of both devices are left unconnected or used as user I/O pins when configuring the same
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect the MSEL pins,
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[7..0] and DCLK must fit the maximum
You can use a single configuration chain to configure Cyclone IV devices with other
Altera devices that support FPP configuration. To ensure that all devices in the chain
complete configuration at the same time or that an error flagged by one device starts
reconfiguration in all devices, tie all the CONF_DONE and nSTATUS pins together.
For more information about configuring multiple Altera devices in the same
configuration chain, refer to
Configuration Handbook.
(MAX II Device or
Microprocessor)
External Host
V
configuration data into multiple devices.
refer to
overshoot outlined in
ADDR
CC
must be high enough to meet the V
Figure
Memory
Table 8–4 on page 8–8
DATA[7..0]
shows multi-device FPP configuration when both Cyclone IV devices are
8–21:
10 k
V
Equation 8–1 on page
CCIO
(1) V
10 k
and
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
CCIO
Configuring Mixed Altera FPGA Chains
Table 8–5 on page
GND
IH
(1)
specification of the I/O on the device and the external host.
Buffers (4)
8–5.
CONF_DONE
nSTATUS
nCE
DATA[7..0] (4)
nCONFIG
DCLK (4)
Cyclone IV Device 1
8–9. Connect the MSEL pins directly to V
MSEL[3..0]
nCEO
(3)
N.C. (2)
© December 2010 Altera Corporation
GND
Cyclone IV Device 2
CONF_DONE
nSTATUS
nCE
DATA[7..0] (4)
nCONFIG
DCLK (4)
in volume 2 of the
MSEL[3..0]
CCA
nCEO
or GND.
Configuration
N.C. (2)
(3)