EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 203

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
© December 2010 Altera Corporation
The programming hardware or download cable then places the configuration data
one bit at a time on the DATA[0] pin of the device. The configuration data is clocked
into the target device until CONF_DONE goes high. The CONF_DONE pin must have an
external 10-k pull-up resistor for the device to initialize.
When you use a download cable, setting the Auto-restart configuration after error
option does not affect the configuration cycle because you must manually restart
configuration in the Quartus II software if an error occurs. Additionally, the Enable
user-supplied start-up clock (CLKUSR) option has no effect on device initialization,
because this option is disabled in the .sof when programming the device with the
Quartus II Programmer and download cable. Therefore, if you turn on the CLKUSR
option, you do not have to provide a clock on CLKUSR when you configure the device
with the Quartus II Programmer and a download cable.
Figure 8–17
Figure 8–17. PS Configuration Using a Download Cable
Notes to
(1) You must connect the pull-up resistor to the same supply voltage as the V
(2) The pull-up resistors on DATA[0] and DCLK are only required if the download cable is the only configuration
(3) Pin 6 of the header is a V
(4) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(5) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect the MSEL pins,
(6) Power up the V
scheme used on your board. This is to ensure that DATA[0] and DCLK are not left floating after configuration. For
example, if you also use a configuration device, the pull-up resistors on DATA[0] and DCLK are not required.
device. For this value, refer to the
ByteBlaster II, ByteBlaster MV, and EthernetBlaster, this pin is a no connect.
refer to
Connect the MSEL pins directly to V
Third-party programmers must switch to 2.5 V. Pin 4 of the header is a V
The MasterBlaster cable can receive power from either 5.0- or 3.3-V circuit boards, DC power supply, or 5.0 V from
the USB cable. For this value, refer to the
10 kΩ
(2)
V
Figure
CCA
Table 8–3 on page
(1)
shows PS configuration for Cyclone IV devices with a download cable.
8–17:
(2)
V
CC
CCA
of the ByteBlaster II, USB-Blaster, or ByteBlasterMV cable with a 2.5-V supply from V
(1)
10 kΩ
V
CCA
IO
(1)
8–8,
10 kΩ
reference voltage for the MasterBlaster output driver. V
Table 8–4 on page
GND
MasterBlaster Serial/USB Communications Cable User
CCA
or GND.
nCE
DCLK
DATA[0]
nCONFIG
MSEL[ ] (5)
MasterBlaster Serial/USB Communications Cable User
Cyclone IV Device
CONF_DONE
8–8, and
nSTATUS
nCEO
Table 8–5 on page 8–9
N.C. (4)
V
CC
CCA
power supply for the MasterBlaster cable.
CCA
10 kΩ
(1)
Cyclone IV Device Handbook, Volume 1
supply.
V
CCA
IO
10 kΩ
for PS configuration schemes.
(1)
must match the V
Download Cable 10-Pin Male
Pin 1
Guide. With the USB-Blaster,
Header (Top View)
Shield
GND
Guide.
V
CCA
V
IO
CCA
(6)
CCA
(3)
GND
of the
.
8–37