EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 375

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Cyclone IV Reset Control and Power Down
Transceiver Reset Sequences
Figure 2–5. Sample Reset Sequence for Bonded Configuration Receiver and Transmitter Channels—Receiver CDR in Manual
Lock Mode
Notes to
(1) For t
(2) The number of rx_locktorefclk[n] and rx_locktodata[n] signals depend on the number of channels configured. n=number of
(3) For t
(4) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In subsequent reset sequences, the
© December 2010 Altera Corporation
(rxurstpma) rx_analogreset
channels.
busy signal is asserted and deasserted only if there is a read or write operation to the ALTGX_RECONFIG megafunction.
(rxurstpcs) rx_digitalreset
(txurstpcs) tx_digitalreset
Output Status Signals
CDR Control Signals
rx_locktorefclk[n] (2)
LTD_Manual
LTR_LTD_Manual
Figure
rx_locktodata[n] (2)
rx_locktorefclk[0]
rx_locktodata[0]
Reset Signals
2–5:
pll_locked
pll_areset
duration, refer to the
busy (4)
duration, refer to the
1
Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
This configuration contains both a transmitter and receiver channel. When the
receiver CDR is in manual lock mode, use the reset sequence shown in
As shown in
in manual lock mode configuration:
1. After power up, assert pll_areset for a minimum period of 1 s (the time
2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and
between markers 1 and 2).
rx_locktorefclk signals asserted and the rx_locktodata signal deasserted
during this time period. After you deassert the pll_areset signal, the
multipurpose PLL starts locking to the input reference clock.
1 µs
Cyclone IV Device Datasheet
2
Cyclone IV Device Datasheet
Figure
3
2–5, perform the following reset procedure for the receiver CDR
Two parallel clock cycles
4
5
chapter.
6
chapter.
t
LTR_LTD_Manual
(3)
7
7
7
7
t
LTD_Manual
(1)
Cyclone IV Device Handbook, Volume 2
8
Figure
2–5.
2–9