EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 196

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

8–30
Cyclone IV Device Handbook, Volume 1
f
1
Programming Parallel Flash Memories
Supported parallel flash memories are external non-volatile configuration devices.
They are industry standard microprocessor flash memories. For more information
about the supported families for the commodity parallel flash, refer to
page
Cyclone IV E devices in a single- or multiple-device chain support in-system
programming of a parallel flash using the JTAG interface with the flash loader
megafunction. The board intelligent host or download cable uses the four JTAG pins
on Cyclone IV E devices to program the parallel flash in system, even if the host or
download cable cannot access the configuration pins of the parallel flash.
For more information about using the JTAG pins on Cyclone IV E devices to program
the parallel flash in-system, refer to
(PFL) with the Quartus II
In the AP configuration scheme, the default configuration boot address is 0×010000
when represented in 16-bit word addressing in the supported parallel flash memory
(Figure
0×020000 because it is represented in 8-bit byte addressing. Cyclone IV E devices
configure from word address 0×010000, which is equivalent to byte address 0×020000.
The Quartus II software uses byte addressing for the default configuration boot
address. You must set the start address field to 0×020000.
The default configuration boot address allows the system to use special parameter
blocks in the flash memory map. Parameter blocks are at the top or bottom of the
memory map.
configuration scheme. You can change the default configuration default boot address
0×010000 to any desired address using the APFC_BOOT_ADDR JTAG instruction. For
more information about the APFC_BOOT_ADDR JTAG instruction, refer to
Instructions” on page
8–21.
8–12). In the Quartus II software, the default configuration boot address is
Figure 8–12
8–56.
Software.
shows the configuration boot address in the AP
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
AN 478: Using FPGA-Based Parallel Flash Loader
© December 2010 Altera Corporation
Table 8–8 on
“JTAG
Configuration