EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 341

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
XAUI Mode
© December 2010 Altera Corporation
1
Clock Frequency Compensation
In Serial RapidIO mode, the rate match FIFO compensates up to ±100 PPM (200 PPM
total) difference between the upstream transmitter and the local receiver reference
clock.
Rate matcher is an optional block available for selection in Serial RapidIO mode.
However, this block is not fully compliant to the SRIO specification. When enabled in
the ALTGX MegaWizard Plug-In Manager, the default settings are:
■
■
■
■
When enabled, the rate match FIFO operation begins after the link is synchronized
(indicated by assertion of rx_syncstatus from the word aligner). When the rate
matcher receives either of the two 10-bit control patterns followed by the respective
10-bit skip pattern, it inserts or deletes the 10-bit skip pattern as necessary to avoid the
rate match FIFO from overflowing or under-running. The rate match FIFO can
delete/insert a maximum of one skip pattern from a cluster.
The rate match FIFO may perform multiple insertion or deletion if the PPM difference
is more than the allowable 200 PPM range. Ensure that the PPM difference in your
system is less than 200 PPM.
XAUI mode provides the bonded (×4) transceiver channel datapath configuration for
XAUI protocol implementation. The Cyclone IV GX transceivers configured in XAUI
mode provides the following functions:
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■
■
■
■
■
The XAUI is a self-managed interface to transparently extend the physical reach of the
XGMII between the reconciliation sublayer and the PHY layer in the 10 Gbps LAN as
shown in
3.125 Gbps with 8B/10B encoded data for a total of actual 10 Gbps data throughput.
At the transmit side of the XAUI interface, the data and control characters are
converted within the XGMII extender sublayer into an 8B/10B encoded data stream.
Each data stream is then transmitted across a single differential pair running at 3.125
Gbps. At the XAUI receiver, the incoming data is decoded and mapped back to the 32-
bit XGMII format. This provides a transparent extension of the physical reach of the
XGMII and also reduces the interface pin count.
control pattern 1 = K28.5 with positive disparity
skip pattern 1 = K29.7 with positive disparity
control pattern 2 = K28.5 with negative disparity
skip pattern 2 = K29.7 with negative disparity
XGMII-to-PCS code conversion at transmitter datapath
PCS-to-XGMII code conversion at receiver datapath
channel deskewing of four lanes
8B/10B encoding and decoding
IEEE P802.3ae-compliant synchronization state machine
clock rate compensation
Figure
1–62. The XAUI interface consists of four lanes, each running at
Cyclone IV Device Handbook, Volume 2
1–61