EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 333

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Table 1–17. Electrical Idle Inference Conditions
© December 2010 Altera Corporation
rx_elecidleinfersel
3'b100
3'b101
3'b101
3'b110
3'b111
[2..0]
1
Electrical Idle Inference
In PIPE mode, the Cyclone IV GX transceiver supports inferring the electrical idle
condition at each receiver instead of detecting the electrical idle condition using
analog circuitry, as defined in the version 2.0 of PCIe Base Specification. The inference
is supported using rx_elecidleinfersel[2..0] port, with valid driven values
as listed in
The electrical idle inference module drives the pipeelecidle signal high in each
receiver channel when an electrical idle condition is inferred. The electrical idle
inference module cannot detect electrical idle exit condition based on the reception of
the electrical idle exit ordered set, as specified in the PCI Express (PIPE) Base
Specification.
When enabled, the electrical idle inference block uses electrical idle ordered set
detection from the fast recovery circuitry to drive the pipeelecidle signal.
Compliance Pattern Transmission
In PIPE mode, the Cyclone IV GX transceiver supports compliance pattern
transmission which requires the first /K28.5/ code group of the compliance pattern to
be encoded with negative current disparity. This requirement is supported using a
tx_forcedispcompliance port that when driven with logic high, the transmitter
data on the tx_datain port is transmitted with negative current running disparity.
The compliance pattern is a repeating sequence of the four code groups: /K28.5/;
/D21.5/; /K28.5/; /D10.2/.
where the tx_forcedispcompliance port must be asserted in the same parallel
clock cycle as /K28.5/D21.5/ of the compliance pattern on tx_datain[15..0]
port.
L0
Recovery.RcvrCfg
Recovery.Speed when
successful speed
negotiation = 1'b1
Recovery.Speed when
successful speed
negotiation = 1'b0
Loopback.Active (as slave) Absence of an exit from electrical idle in 128 s window
Link Training and Status
State Machine State
Table 1–17
in each link training and status state machine substate.
Absence of update_FC or alternatively skip ordered set in 128 s
window
Absence of TS1 or TS2 ordered set in 1280 UI interval
Absence of TS1 or TS2 ordered set in 1280 UI interval
Absence of an exit from electrical idle in 2000 UI interval
Figure 1–53
shows the compliance pattern transmission
Description
Cyclone IV Device Handbook, Volume 2
1–53