EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 303

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Receiver Channel Datapath
RX Phase Compensation FIFO
© December 2010 Altera Corporation
1
The byte ordering block operates in either word-alignment-based byte ordering or
user-controlled byte ordering modes.
In word-alignment-based byte ordering mode, the byte ordering block starts looking
for the byte ordering pattern in the byte-deserialized data and restores the order if
necessary when it detects a rising edge on the rx_syncstatus signal. Whenever the
byte ordering pattern is found, the rx_byteorderalignstatus signal is asserted
regardless if the pad byte insertion is necessary. If the byte ordering block detects
another rising edge on the rx_syncstatus signal from the word aligner, it deasserts
the rx_byteorderalignstatus signal and repeats the byte ordering operation.
In user-controlled byte ordering mode, the byte ordering operation is user-triggered
using rx_enabyteord port. A rising edge on rx_enabyteord port triggers the byte
ordering block to start looking for the byte ordering pattern in the byte-deserialized
data and restores the order if necessary. When the byte ordering pattern is found, the
rx_byteorderalignstatus signal is asserted regardless if a pad byte insertion is
necessary.
The RX phase compensation FIFO compensates for the phase difference between the
parallel receiver clock and the FPGA fabric interface clock, when interfacing the
receiver channel to the FPGA fabric (directly or through the PIPE and PCIe hard IP
blocks). The FIFO is four words deep, with latency between two to three parallel clock
cycles.
Figure 1–24
Figure 1–24. RX Phase Compensation FIFO Block Diagram
Note to
(1) Parameter x refers to the transceiver channel width, where 8, 10, 16, or 20 bits are supported.
The FIFO can operate in registered mode, contributing to only one parallel clock cycle
of latency in the Deterministic Latency functional mode. For more information, refer
to
clocking, refer to
Miscellaneous Receiver PCS Feature
The receiver PCS supports the following additional feature:
■
“Deterministic Latency Mode” on page
Output bit-flip—reverses the bit order at a byte level at the output of the receiver
phase compensation FIFO. For example, if the 16-bit parallel receiver data at the
output of the receiver phase compensation FIFO is '10111100 10101101'
(16'hBCAD), enabling this option reverses the data on rx_dataout port to
'00111101 10110101' (16'h3DB5).
Figure
1–24:
shows the RX phase compensation FIFO block diagram.
“FPGA Fabric-Transceiver Interface Clocking” on page
wr_clk
Compensation
RX Phase
FIFO
rd_clk
1–68. For more information about FIFO
rx_phase_comp_fifo_error
rx_dataout[x..0] (1)
Cyclone IV Device Handbook, Volume 2
1–39.
1–23