EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 182

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

8–16
Figure 8–5. Multi-Device AS Configuration in Which Devices Receive the Same Data with a Single .sof
Notes to
(1) Connect the pull-up resistors to the V
(2) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device of the Cyclone IV device
(4) Connect the series resistor at the near end of the serial configuration device.
(5) Connect the repeater buffers between the master and slave devices for DATA[0] and DCLK. All I/O inputs must maintain a maximum AC voltage
(6) The 50- series resistors are optional if the 3.3-V configuration voltage standard is applied. For optimal signal integrity, connect these 50- series
(7) These pins are dual-purpose I/O pins. The nCSO pin functions as FLASH_nCE pin in AP mode. The ASDO pin functions as DATA[1] pin in AP
(8) Only Cyclone IV GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK.
Cyclone IV Device Handbook, Volume 1
Serial Configuration
in AS mode and the slave devices in PS mode. To connect the MSEL pins for the master device in AS mode and slave devices in PS mode, refer
to
of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in
Requirements” on page
resistors if the 2.5- or 3.0-V configuration voltage standard is applied.
and FPP modes.
Device
Table 8–3 on page
Figure
DCLK
DATA
ASDI
nCS
50 Ω
8–5:
25 Ω
(4),(6)
(4)
GND
10 kΩ
8–8,
Single SRAM Object File
The second method configures both the master device and slave devices with the
same .sof. The serial configuration device stores one copy of the .sof. You must set up
one or more slave devices in the chain. All the slave devices must be set up in the
same way
In this setup, all the Cyclone IV devices in the chain are connected for concurrent
configuration. This reduces the AS configuration time because all the Cyclone IV
devices are configured in one configuration cycle. Connect the nCE input pins of all
the Cyclone IV devices to GND. You can either leave the nCEO output pins on all the
Cyclone IV devices unconnected or use the nCEO output pins as normal user I/O
pins. The DATA and DCLK pins are connected in parallel to all the Cyclone IV devices.
V
8–5.
CCIO
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
nCSO (7)
ASDO (7)
Table 8–4 on page
Cyclone IV Master Device
(1)
10 kΩ
V
CCIO
50 Ω
CCIO
(Figure
Buffers (5)
(1)
(7)
supply of the bank in which the pin resides.
CLKUSR
MSEL[ ]
10 kΩ
nCEO
8–8, and
V
CCIO
8–5).
(1)
N.C. (2)
(3)
Table 8–5 on page
(9)
GND
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
Cyclone IV Slave Device 1
8–9. Connect the MSEL pins directly to V
MSEL[ ]
nCEO
N.C. (2)
(3)
GND
© December 2010 Altera Corporation
“Configuration and JTAG Pin I/O
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
Cyclone IV Slave Device 2
CCA
or GND.
MSEL[ ]
nCEO
Configuration
N.C. (2)
(3)