EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 349

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
© December 2010 Altera Corporation
f
Figure 1–67
Figure 1–67. Transceiver Configuration in Deterministic Latency Mode
Both CPRI and OBSAI protocols define the serial interface connecting the base station
component (specifically channel cards) and remote radio heads (specifically radio
frequency cards) in a radio base station system with fiber optics. The protocols require
the accuracy of round trip delay measurement for single-hop and multi-hop
connections to be within ± 16.276 ns. The Cyclone IV GX transceivers support the
following CPRI and OBSAI line rates using Deterministic Latency mode:
■
■
For more information about deterministic latency implementation, refer to
Implementing Deterministic Latency for CPRI and OBSAI Protocols in Stratix IV, HardCopy
IV, Arria II GX, and Cyclone IV
CPRI —614.4 Mbps, 1.2288 Gbps, 2.4576 Gbps, and 3.072 Gbps
OBSAI—768 Mbps, 1.536 Gbps, and 3.072 Gbps
Functional Mode
Channel Bonding
Low-Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency (MHz)
Data Rate (Gbps)
shows the transceiver configuration in Deterministic Latency mode.
Disabled
Enabled
156.25
16-Bit
3.125
0.6-
60-
Disabled
Devices.
Enabled
Disabled
Disabled
1.5625
156.25
8-Bit
Manual Alignment
0.6-
30-
(10-Bit)
Disabled
Enabled
20-Bit
156.25
3.125
0.6-
60-
Disabled
Disabled
Disabled
Deterministic Latency
Disabled
1.5625
10-Bit
156.25
0.6-
30-
Disabled
×1, ×4
Disabled
Enabled
156.25
16-Bit
3.125
0.6-
60-
Cyclone IV Device Handbook, Volume 2
Enabled
Disabled
Disabled
Disabled
1.5625
156.25
8-Bit
0.6-
30-
(10-Bit)
Bit Slip
Disabled
Enabled
156.25
20-Bit
3.125
0.6-
60-
Disabled
Disabled
AN 610:
Disabled
Disabled
156.25
1.5625
10-Bit
0.6-
30-
1–69