EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 179

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
Figure 8–3. Multi-Device AS Configuration
Notes to
(1) Connect the pull-up resistors to the V
(2) Connect the pull-up resistor to the V
(3) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device of the Cyclone IV device
(5) Connect the series resistor at the near end of the serial configuration device.
(6) Connect the repeater buffers between the master and slave devices of the Cyclone IV device for DATA[0] and DCLK. All I/O inputs must maintain
(7) The 50- series resistors are optional if the 3.3-V configuration voltage standard is applied. For optimal signal integrity, connect these 50- series
(8) These pins are dual-purpose I/O pins. The nCSO pin functions as FLASH_nCE pin in AP mode. The ASDO pin functions as DATA[1] pin in AP
(9) Only Cyclone IV GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK.
© December 2010 Altera Corporation
in AS mode and the slave devices in PS mode. To connect the MSEL pins for the master device in AS mode and slave devices in PS mode, refer
to
a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in
and JTAG Pin I/O Requirements” on page
resistors if the 2.5- or 3.0-V configuration voltage standard is applied.
and FPP modes.
Table 8–3 on page
Serial Configuration
Figure
Device
8–3:
1
DCLK
DATA
ASDI
nCS
10 kΩ
V
CCIO
8–8,
25 Ω
50 Ω (5), (7)
The first Cyclone IV device in the chain is the configuration master and it controls the
configuration of the entire chain. Other Altera devices that support PS configuration
can also be part of the chain as configuration slaves.
In the multi-device AS configuration, the board trace length between the serial
configuration device and the master device of the Cyclone IV device must follow the
recommendations in
(1)
Table 8–4 on page
(5)
10 kΩ
V
CCIO
CCIO
(1)
CCIO
10 kΩ
supply voltage of I/O bank in which the nCE pin resides.
GND
supply of the bank in which the pin resides.
8–5.
V
CCIO
8–8, and
(1)
DATA[0]
DCLK
nCSO (8)
ASDO (8)
nSTATUS
CONF_DONE
nCONFIG
nCE
Cyclone IV Master Device
Table 8–6 on page
Buffers (6)
50 Ω (7)
Table 8–5 on page
CLKUSR
MSEL[ ]
nCEO
8–9. Connect the MSEL pins directly to V
8–17.
10 kΩ
(9)
(4)
V
CCIO
(2)
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
Cyclone IV Slave Device
Cyclone IV Device Handbook, Volume 1
MSEL[ ]
nCEO
CCA
or GND.
“Configuration
N.C. (3)
(4)
8–13