EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 330

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–50
Cyclone IV Device Handbook, Volume 2
Table 1–15. Transceiver-FPGA Fabric Interface Ports in PIPE Mode
Receiver Detection Circuitry
In PIPE mode, the transmitter supports receiver detection function with a built-in
circuitry in the transmitter PMA. The PCIe protocol requires the transmitter to detect
if a receiver is present at the far end of each lane as part of the link training and
synchronization state machine sequence. This feature requires the following
conditions:
■
■
■
The circuit works by sending a pulse on the common mode of the transmitter. If an
active PCIe receiver is present at the far end, the time constant of the step voltage on
the trace is higher compared to when the receiver is not present. The circuitry
monitors the time constant of the step signal seen on the trace to decide if a receiver
was detected.
Figure 1–50
and unsuccessful receiver detection scenarios respectively. The tx_forceelecidle
port must be asserted at least 10 parallel clock cycles prior to assertion of
tx_detectrxloop port to ensure the transmitter buffer is properly tri-stated.
Detection completion is indicated by pipephydonestatus assertion, with detection
successful indicated by 3'b011 on pipestatus[2..0] port, or detection
unsuccessful by 3'b000 on pipestatus[2..0] port.
Notes to
(1) When used with PCIe hard IP block, the byte SERDES is not used. In this case, the data ports are 8 bits wide and
(2) Cyclone IV GX transceivers do not implement power saving measures in lower power states (P0s, P1, and P2),
tx_datain[15..0]
tx_ctrlenable[1..0]
rx_dataout[15..0]
rx_ctrldetect[1..0]
tx_detectrxloop
tx_forceelecidle
tx_forcedispcompliance
pipe8b10binvpolarity
powerdn[1..0]
pipedatavalid
pipephydonestatus
pipeelecidle
pipestatus
transmitter output buffer to be tri-stated
have OCT utilization
125 MHz clock on the fixedclk port
control identifier is 1 bit wide.
except when putting the transmitter buffer in electrical idle in the lower power states.
Table
Transceiver Port Name
and
1–15:
Figure 1–51
(2)
(1)
(1)
(1)
(1)
show the detection mechanism example for a successful
TxData[15..0]
TxDataK[1..0]
RxData[15..0]
RxDataK[1..0]
TxDetectRx/Loopback
TxElecIdle
TxCompliance
RxPolarity
PowerDown[1..0]
RxValid
PhyStatus
RxElecIdle
RxStatus[2..0]
Chapter 1: Cyclone IV Transceivers Architecture
PIPE 2.00 Port Name
© December 2010 Altera Corporation
Transceiver Functional Modes