EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 311

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
Figure 1–33. Transmitter Only Datapath Clocking in Non-Bonded Channel Configuration
Figure 1–34. Receiver Only Datapath Clocking without Rate Match FIFO in Non-Bonded Channel Configuration
Note to
(1) High-speed recovered clock.
© December 2010 Altera Corporation
tx_clkout
rx_clkout
rx_coreclk
rx_dataout
tx_coreclk
Fabric
Fabric
FPGA
FPGA
tx_datain
Figure 1–34
:
Figure 1–34
receiver PCS supports configuration without the rate match FIFO. The CDR unit in
the channel recovers the clock from the received serial data and generates the high-
speed recovered clock for the deserializer, and low-speed recovered clock for
forwarding to the receiver PCS. The low-speed recovered clock feeds to the following
blocks in the receiver PCS:
■
■
■
■
■
When the byte deserializer is enabled, the low-speed recovered clock frequency is
halved before feeding into the write clock of the RX phase compensation FIFO. The
low-speed recovered clock is available in the FPGA fabric as rx_clkout port, which
can be used in the FPGA fabric to capture receiver data and status signals.
When the transceiver is configured for transmitter and receiver operation in
non-bonded channel configuration, the receiver PCS supports configuration with and
without the rate match FIFO. The difference is only at the receiver datapath clocking.
The transmitter datapath clocking is identical to transmitter only operation mode as
shown in
word aligner
8B/10B decoder
write clock of byte deserializer
byte ordering
write clock of RX phase compensation FIFO
Figure
Phase
Comp
FIFO
Rx
shows the datapath clocking in receiver only operation. In this mode, the
wr_clk
Tx Phase
Comp
FIFO
1–33.
rd_clk
Order-
Byte
ing
/2
serializer
Byte
De-
wr_clk
Byte Serializer
/2
Transmitter Channel PCS
Decoder
8B/10B
rd_clk
Receiver Channel PCS
Match
Rate
FIFO
8B/10B Encoder
Deskew
FIFO
Cyclone IV Device Handbook, Volume 2
Aligner
Word
Deserial-
Transmitter Channel PMA
Receiver Channel PMA
izer
Serializer
(1)
low-speed recovered clock
1–31
CDR
low-speed clock
high-speed
clock
CDR clock